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| motorola semiconductor technical data DSP96002 order this document by: DSP96002/d, rev. 2 ?996 motorola, inc. 32-bit general purpose floating-point dual-port processor the DSP96002 is designed to support intensive graphic image and numeric processing. it is a dual-port, low-power, general purpose floating-point processor. the dsp includes 1024 words of data ram (equally divided into x data and y data memory), 1024 words of full- speed on-chip program ram, two data roms, a dual-channel direct memory access (dma) controller, special on-chip bootstrap hardware, and on-chip emulation (once ) debug circuitry. the central processing unit (cpu) consists of three 32-bit execution units operating in parallel. the DSP96002 has two identical memory expansion ports with control lines to facilitate interfacing srams, drams (operating in their fast access modes), and video rams (vrams). each port can be configured as a host interface (hi), which facilitates easy interface with other processors for multiprocessor applications. linear arrays of DSP96002s can be implemented without glue logic. the mpu-style programming model and instruction set allow straightforward generation of efficient, compact code. the high speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive applications that require floating-point processing and access to large memory subsystems. figure 1 block diagram internal switch and bit manipulation unit program controller data yab xab pab ydb xdb pdb gdb program decode controller program address generator program interrupt controller clock generator ddb dual channel dma controller debug controller 4 serial debug port modb/irqb moda/irqa reset external address switch address generation unit (agu) ?ieee floating point ?32 32 integer alu clk memory 512 32 ram memory 512 32 ram program 1024 32 ram and 64 32 bootstrap rom 512 32? rom 512 32? rom data alu 32-bit buses address external address switch bus control control external data switch port b memory x data y data 32 modc/irqc bus control control host interface data 32 * ** * * * * dual access (dma/core) 4 4 18 18 instruction cache timer timer port a 32 address 32 1024 32 virtual locations ? 32-bit host interface 32-bit once aa0306 bus external data switch bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ii DSP96002/d, rev. 2 motorola table of contents section 1 signal/connection descriptions . . . . . . . . . . . . . . . . . . 1-1 section 2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 section 3 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 section 4 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 section 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 appendix a bootstrap code for DSP96002. . . . . . . . . . . . . . . . . . . . . a-1 appendix b x and y memory rom tables . . . . . . . . . . . . . . . . . . . . . . . b-1 for technical assistance: telephone: 1-800-521-6274 email: dsphelp@dsp.sps.mot.com internet: http://www.motorola-dsp.com data sheet conventions t his data sheet uses the following conventions: overbar used to indicate a signal that is active when pulled low (for example, the reset pin is active when low.) ?sserted means that a high true (active high) signal is high or that a low true (active low) signal is low ?easserted means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol note: values for v il , v ol , v ih , and v oh are defined by individual product specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . DSP96002 features motorola DSP96002/drev. 2 iii features digital signal processing core efficient 32-bit dsp engine conforms to ieee 754-1985 standard for single precision (32-bit) and single extended precision (44-bit) arithmetic up to 30 million instructions per second (mips) at 60 mhz parallel operation of data alu, address generation unit (agu), and program controller within the cpu allow more processing per instruction cycle single-cycle 32 32 bit parallel multiplier e highly parallel instruction set with unique dsp addressing modes e nested hardware do loops e instruction cache extended to operate as 4 k byte (1 k word) e fast auto-return interrupts e address buses: one 32-bit unidirectional internal x memory address bus (xab) one 32-bit unidirectional internal y memory address bus (yab) one 32-bit internal program address bus (pab) two 32-bit external address buses e data buses: one 32-bit bidirectional internal x memory data bus (xdb) one 32-bit bidirectional internal y memory data bus (ydb) one 32-bit bidirectional internal global memory data bus (gdb) one 32-bit bidirectional internal dma data bus (ddb) one 32-bit bidirectional internal program data bus (pdb) two 32-bit external data buses e mcu-like instruction set mnemonics make programming easier memory e on-chip 1024 32-bit program ram e two independent on-chip 512 32-bit data rams e two independent on-chip 512 32-bit data roms (1024 32-bit virtual memory) e on-chip 64 32-bit bootstrap rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . DSP96002 product documentation iv DSP96002/drev. 2 motorola off-chip expansion to 2 2 32 32-bit words of data memory e off-chip expansion to 2 32 32-bit words of program memory miscellaneous features e two expansion ports assignable to x data, y data, or program memory spaces or a combination thereof, effectively doubling off-chip bus bandwidth. e host interface circuitry on each port provides a flexible slave interface to direct memory access (dma) controllers and external processors for easy design of multimaster systems e write strobe pins support interface to external srams without additional logic e two programmable timers/counters e three external interrupt/mode control lines e one external reset line for hardware reset e 4-pin once port for unobtrusive, processor speed-independent debugging e hcmos design for operating frequencies from 60 mhz down to dc e 223-pin plastic pin grid array (pga) package or 240-pin ceramic quad flat pack (cqfp) package e 5.0 v power supply product documentation the two manuals listed in table 1 are required for a complete description of the DSP96002 and are necessary to design properly with the device. documentation is available from a local motorola distributor, a motorola semiconductor sales office, a motorola literature distribution center, or through the motorola dsp home page on the internet (the source for the latest information). table 1 additional documentation document name description order number DSP96002 user? manual detailed description of the DSP96002 core processor and peripherals DSP96002um/ad DSP96002 data sheet electrical and timing specifications, and pin and package descriptions DSP96002/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola DSP96002/d, rev. 2 1-1 section 1 signal/connection descriptions signal groupings the input and output signals of the DSP96002 are organized into eight functional groups, as shown in table 1-1 and as illustrated in figure 1-1 . figure 1-1 is a diagram of DSP96002 signals by functional group. table 1-1 DSP96002 functional signal groupings functional group detailed description power (v ccn and v ccq ) table 1-2 ground (gnd n and gnd q ) table 1-3 clock (clk) table 1-4 interrupt and mode control table 1-5 port a (address, data, and control) table 1-6 port b (address, data, and control) table 1-6 timer/event counters table 1-7 once port table 1-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions signal groupings 1-2 DSP96002/d, rev. 2 motorola figure 1-1 functional group pin allocations address bus a aa0?a31 data bus a ad0?d31 port a bus control as1 as0 ar/w abs abl att ats ata aae ade ahs aha ahr abr abg abb aba interrupt and mode control moda/irqa modb/irqb modc/irqc reset clock input clk power 1 v ccn v ccq address bus b ba0?a31 data bus b bd0 ?bd31 port b bus control bs1 bs0 br/w bbs bbl btt bts bta bae bde bhs bha bhr br bbg bbb bba on-chip emulation port (once) dso dsi/oso dsck/os1 dr DSP96002 32 / 32 / 32 / 32 / awr bwr timer/event counters tio0?io1 2 ground 2 gnd n gnd q note: 1. number of power input pins is package dependent. see section 3 . 2. number of ground connections is package dependent. see section 3 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions power motorola DSP96002/d, rev. 2 1-3 power ground table 1-2 power inputs power name description v ccn normal power ? ccn inputs are v cc provided for general use with the DSP96002 peripheral circuits. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v ccq quiet power v ccq inputs provide isolated power for the internal processing logic. the voltage should be well-regulated, and the input should be provided with an extremely low impedance path to the v cc power rail. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. note: the number of available power connecctions is package-dependent. see section 3 for a detailed description of individual package pinouts. table 1-3 grounds ground name description gnd n normal ground ?nd p connections provide a ground return for the DSP96002 peripheral circuits. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd q quiet ground ?nd q is an isolated ground for the internal processing logic. the connection should be provided with an extremely low-impedance path to ground. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. note: the number of available ground connecctions is package-dependent. see section 3 for a detailed description of individual package pinouts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions clock 1-4 DSP96002/d, rev. 2 motorola clock table 1-4 clock signal signal name type state during reset signal description clk input input clock input ?lk is a high frequency processor clock input. the frequency is twice the instruction rate. as shown in figure 1-2 , an internal phase generator divides clk into four phases (t 0 , t 1 , t 2 and t 3 ), which is the basic instruction execution cycle. additional t w phases are optionally generated to insert wait states (ws) into instruction execution. a wait state is formed by pairing a t 2 and t w phase. clk should be continuous with a 46 54% duty cycle. figure 1-2 clock input and instruction cycle timing two wait states no wait states t 0 t 1 t 2 t 3 t w t 0 t 1 t 2 t 2 t 2 t w t 3 clk instruction cycle instruction cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions interrupt and mode control motorola DSP96002/d, rev. 2 1-5 interrupt and mode control table 1-5 interrupt and mode control signal name type state during reset signal description reset input input reset ?his input is a direct hardware reset of the processor. when reset is asserted low, the signal is internally synchronized to the input clock (clk), the dsp is placed in the reset state, and the internal phase generator is reset. a schmitt trigger input is used for noise immunity and allows a slowly rising input (such as a capacitor charging) to reliably reset the chip. if reset is deasserted synchronous to the input clock (clk), exact start-up timing is guaranteed, allowing multiple processors to start-up synchronously and operate together in ?ock-step.?when the reset pin is deasserted, the initial chip operating mode is latched from the moda, modb and modc pins. moda/irqa input input mode select a/external interrupt request a ?his input is internally synchronized to the input clock (clk). moda/irqa selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb and modc select one of eight initial chip operating modes latched into the operating mode register (omr) when the reset pin is deasserted. if irqa is asserted synchronous to the input clock (clk), multiple processors can be resynchronized by using the wait instruction and asserting irqa to exit the wait state. if the processor is in the stop standby state and irqa is asserted, the processor will exit the stop state. modb/ irqb input input mode select b/external interrupt request b ?his input is internally synchronized to the input clock (clk). modb/irqb selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb and modc select one of eight initial chip operating modes latched into the operating mode register (omr) when the reset pin is deasserted. if irqb is asserted synchronous to the input clock (clk), multiple processors can be resynchronized by using the wait instruction and asserting irqb to exit the wait state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b 1-6 DSP96002/d, rev. 2 motorola port a and port b port a and port b are identical in pinout and function. the following pin descriptions apply to both ports. each port may be a bus master and each port has a slave host interface which can be accessed on demand. modc/irqc input input mode select c/external interrupt request c this input is internally synchronized to the input clock (clk). modc/irqc selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb and modc select one of eight initial chip operating modes latched into the operating mode register (omr) when the reset pin is deasserted. if irqc is asserted synchronous to the input clock (clk), multiple processors can be resynchronized by using the wait instruction and asserting irqc to exit the wait state. table 1-6 port a and port b signal name type state during reset signal description aa0?a31 ba0?a31 input or output tri-stated address bus a0?31 specify the address for external program and data memory accesses. if there is no external bus activity, a0?31 remain at their previous values. the address enable (ae ) input acts as an output enable control for a0?31. a0?31 are stable whenever the transfer strobe ts is asserted and may change only when ts is deasserted. the signal direction depends on whether the dsp is the bus master: bus master ?0?31 are tri-state, active high outputs. not a bus master ?2?5 are active high inputs used to select the host interface register. lines a0 a1 and a6?31 are tri-stated. as inputs, a2?5 may change asynchronously relative to the input clock (clk). table 1-5 interrupt and mode control (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b motorola DSP96002/d, rev. 2 1-7 ad0?d31 bd0?d31 input/ output tri-stated data bus ?0?31 are tri-state, active high, bidirectional input/outputs whether the dsp is a bus master or not. the data enable (de ) input acts as an output enable control for d0?31. as a bus master, the data lines are controlled by the cpu instruction execution or the dma controller. d0 d31 are also the host interface data lines. if there is no external bus activity, d0?31 are tri-stated. as0 ?s1 bs0 ?s1 output tri-stated space select these signals can be viewed in different ways, depending on how the external memories are mapped. they support splitting memory spaces among ports, and mapping multiple memory spaces into the same physical memory locations. s0 and s1 are outputs when the dsp is the bus master and tri-stated when the dsp is not a bus master. timing is the same as the address lines a0 a31. ar/w br/w input or output tri-stated read/write r/w is a an output when the dsp is the bus master and an input when not a bus master. bus master timing is the same as the DSP96002 address lines, giving an ?arly write?signal for dram interfacing. r/w is high for a read access and low for a write access. the r/w pin is also the host interface read/write input. as an input, r/w may change asynchronously relative to the input clock. r/w goes high if the external bus is not used during an instruction cycle. awr bwr output tri-stated write strobe ?r is an output when the dsp is the bus master and tri-stated when it is not a bus master. wr supports a glueless interface to external srams. wr is asserted during external memory write cycles to indicate that the address lines a0?32, s1, s0, bs , bl , and r/w are stable. the output data goes to the data bus after wr is asserted. wr requires a weak external pull-up resistor and can be connected directly to the we pin of a static ram. abs bbs output tri-stated bus strobe bs is an output when the dsp is the bus master and tri-stated when it is not a bus master. bus strobe is asserted at the start of a bus cycle (providing an ?arly bus start?signal for dram interfacing) and deasserted at the end of the bus cycle. the early negation provides an ?arly bus end?signal useful for external bus control. if the external bus is not used during an instruction cycle, bs remains deasserted until the next external bus cycle. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b 1-8 DSP96002/d, rev. 2 motorola att btt output tri-stated transfer type ?t is an output when the dsp is the bus master and tri-stated when it is not a bus master. when the dsp is the bus master, tt is controlled by an on-chip page circuit. tt is asserted when a fast access memory mode (page, static column, nibble or serial shift register) is detected. if the external bus is not used during an instruction cycle, or a fault is detected by the page circuit during an external access, tt remains deasserted. the parameters of the page circuit fault detection are user programmable. ats bts input or output tri-stated transfer strobe ts is an output when the dsp is the bus master and an input when it is not a bus master. when the dsp is the bus master, ts is asserted to indicate that the address lines a0?31, s1, s0, bs , bl and r/w are stable and that a bus read or bus write transfer is taking place. during a read cycle, input data is latched inside the DSP96002 on the rising edge of ts . during a write cycle, output data is placed on the data bus after ts is asserted. therefore, ts can be used as an output enable control for external data bus buffers if they are present. if the external bus is not used during an instruction cycle, ts remains deasserted until the next external bus cycle. an external flip-flop can delay ts , if required, for slow devices or more address decoding time. the ts pin is also the host interface transfer strobe input used to enable the data bus output drivers during host read operations and to latch data inside the host interface during host write operations. as an input, ts may change asynchronously relative to the input clock. write data is latched inside the host interface on the rising edge of ts . when the dsp is the bus master, the combination of bs and ts can be decoded externally to determine the status of the current bus cycle and to generate hardware strobes useful for latching address and data signals. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b motorola DSP96002/d, rev. 2 1-9 ata bta input input, ignored during reset transfer acknowledge the ta input is a synchronous ?tack?function that can extend an external bus cycle indefinitely. ta must be asserted and deasserted synchronously to the input clock (clk) for proper operation. ta is sampled on the falling edge of the input clock (clk). any number of wait states (0, 1, 2, ? infinity) may be inserted by keeping ta deasserted. in a typical operation, ta is first deasserted at the start of a bus cycle, then is asserted to enable completion of the bus cycle, and finally is deasserted before the next bus cycle.the current bus cycle completes one clock period after ta is asserted synchronously to clk. the number of wait states is determined by the ta input or by the bus control register (bcr), whichever is longer. the bcr can be used to set the minimum number of wait states in external bus cycles. if ta is tied low (asserted) and no wait states are specified in the bcr, zero wait states will be inserted into external bus cycles. note: if the DSP96002 is the bus master and there is no external bus activity or the DSP96002 is not the bus master, then the ta input is ignored by the core. aae bae input input, ignored during reset address enable ae is an input that must be asserted and deasserted synchronous to the input clock (clk) for proper operation. if the dsp is the bus master, ae is asserted to enable the a0?31 address output drivers. if ae is deasserted, the address output drivers are tri-stated. if the dsp is not a bus master, the address output drivers are tri- stated regardless of whether ae is asserted or deasserted. the function of ae is to allow implementation of multiplexed bus systems. an example of such an implementation is a multiplexed address1/address2 bus used with dual port memories, such as dynamic vrams. note: there must be at least one undriven clk period between enables for multiplexed buses to allow one bus to tri- state before another bus is enabled. external control is responsible for this timing. for non-multiplexed systems, ae should be tied low. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b 1-10 DSP96002/d, rev. 2 motorola ade bde input input, ignored during reset data enable ?e is an input that must be asserted and deasserted synchronous to the input clock (clk) for proper operation. if a bus master or the host interface is being read, de is asserted to enable the d0?31 data bus output drivers. if de is deasserted, the data bus output drivers are tri-stated. if not a bus master, the data bus output drivers are tri-stated regardless of whether de is asserted or deasserted. read-only bus cycles may be performed even though de is deasserted. the function of de is to allow multiplexed bus systems to be implemented. an example is a multiplexed data1/data2 bus used for long word transfers with one 32-bit wide memory. note: there must be at least one undriven clk period between enables for multiplexed buses to allow one bus to tri- state before another bus is enabled. external control is responsible for this timing. for non-multiplexed systems, de should be asserted (tied low). ahs bhs input input host select hs is an input that may change asynchronous to the input clock. hs is asserted low to enable selection of the host interface functions by the address lines a2?5. if ts is asserted when hs is asserted, a data transfer with the host interface will take place. note: both hs and ha must be tied high to disable the host interface. when ha is asserted, hs is ignored. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b motorola DSP96002/d, rev. 2 1-11 aha b ha input input host acknowledge ?a is an input that may change asynchronously to the input clock. ha is used to acknowledge either an interrupt request or a dma request by the host interface. when the host interface is not in dma mode, asserting ts when ha and hr are asserted will enable the contents of the host interface interrupt vector register (ivr) onto the data bus outputs d0?31. this provides an interrupt acknowledge capability compatible with mc68000 family processors. if the host interface is in dma mode, ha is used as a dma transfer acknowledge input and it is asserted by an external device to transfer data between the host interface registers and an external device. in dma read mode, ha is asserted to read the host interface rx register on the data bus outputs d0?31. in dma write mode, ha is asserted to strobe external data into the host interface tx register. write data is latched into the tx register on the rising edge of ha . ahr bhr output driven high host request hr is an output that is never tri-stated. the host request hr is asserted to indicate that the host interface is requesting service?ither an interrupt request or a dma request?rom an external device. the hr output may be connected to interrupt request input irqa , irqb , or irqc of another DSP96002. the on-chip dma controller channel of the other DSP96002 can select the interrupt request input as a dma transfer request input. abr bbr output driven high bus request ?r is an output that is never tri-stated. br is asserted when the cpu or dma is requesting bus mastership. br is deasserted when the cpu or dma no longer needs the bus. br may be asserted or deasserted independent of whether the DSP96002 is a bus master or a bus slave. bus ?arking?allows br to be deasserted even though the DSP96002 is the bus master (see the description of bus ?arking?in the ba pin description). the rh bit in the bus control register allows br to be asserted under software control even though the cpu or dma does not need the bus. br is typically sent to an external bus arbitrator, which controls the priority, parking, and tenure of each DSP96002 on the same external bus. br is only affected by cpu or dma requests for the external bus, never for the internal bus. during hardware reset, br is deasserted and the arbitration is reset to the bus slave state. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b 1-12 DSP96002/d, rev. 2 motorola abg b bg input input, ignored during reset bus grant ?g is an input that must be asserted/ deasserted synchronous to the input clock (clk) for proper operation. bg is asserted by an external bus arbitration circuit indicating the DSP96002 has become the pending bus master. when bg is asserted, the DSP96002 must wait until bb is deasserted before taking bus mastership. when bg is deasserted, bus mastership is typically given up at the end of the current bus cycle. this may occur in the middle of an instruction, which requires more than one external bus cycle for execution. note: indivisible read-modify-write instructions (bset, bclr, bchg) will not give up bus mastership until the end of the current instruction. bg is ignored during hardware reset. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b motorola DSP96002/d, rev. 2 1-13 aba bba output tri-stated bus acknowledge ?a is an open drain output. when deasserting ba , the DSP96002 drives ba high during half a clk cycle and then disables the active pull-up. in this way, only a weak external pull-up resistor is required to hold the line high. ba may be directly connected to bb in order to obtain the same functionality as the mc68040 bb pin. when bg is asserted, the DSP96002 becomes the pending bus master. it waits until bb is negated by the previous bus master, indicating that the previous bus master is off the bus. the pending bus master asserts ba to become the current bus master. ba is asserted when either the cpu or the dma has taken the bus and is the bus master. while ba is asserted, the DSP96002 is the owner of the bus (the bus master). when ba is deasserted, the DSP96002 is a bus slave. ba may be used as a tri-state enable control for external address, data, and bus control signal buffers. note: a current bus master may keep ba asserted after ceasing bus activity, regardless of whether br is asserted or deasserted. this is called ?us parking?and allows the current bus master to use the bus repeatedly without re- arbitration until some other device wants the bus. the current bus master keeps ba asserted during indivisible read-modify-write bus cycles, regardless of whether bg has been deasserted by the external bus arbitration unit. this form of ?us locking?allows the current bus master to perform atomic operations on shared variables in multitasking and multiprocessor systems. current instructions that perform indivisible read-modify- write bus cycles are bclr, bchg and bset. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions port a and port b 1-14 DSP96002/d, rev. 2 motorola abb b bb input input bus busy bb is an input that must be asserted and deasserted synchronous to the input clock (clk) for proper operation. bb is deasserted when there is no bus master on the external bus. in multiple DSP96002 systems, all bb inputs are tied together and are driven by the logical and of all ba outputs. bb is asserted when a pending bus master becomes the current bus master (directly or indirectly by ba assertion). bb is deasserted by the current bus master (directly or indirectly by ba deassertion) to indicate that it is off the bus and is no longer the bus master. the pending bus master monitors the bb signal until it is deasserted. then the pending bus master asserts ba to become the current bus master, which asserts bb directly or indirectly. note: use of pull-up resistors is recommended. abl bbl output driven high bus lock bl is an output that is never tri-stated. asserted at the start of an external indivisible read-modify-write (rmw) bus cycle (providing an ?arly bus start?signal for dram interfacing) and deasserted at the end of the write bus cycle, bl remains asserted between the read and write bus cycles of the read-modify-write bus sequence. bl can be used to indicate that special memory timing (such as rmw timing for drams) may be used or to ?esource lock?an external multi-port memory for secure semaphore updates. the early negation provides an ?arly bus end? signal useful for external bus control. if the external bus is not used during an instruction cycle, bl remains deasserted until the next external indivisible read-modify-write bus cycle. bl also remains deasserted if the external bus cycle is not an indivisible read-modify-write bus cycle or if there is an internal rmw bus cycle. the only instructions that automatically assert bl are a bset, bclr or bchg instruction, which accesses external memory. bl can also be asserted by setting the lh bit in the bcr. table 1-6 port a and port b (continued) signal name type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions timer/event counter motorola DSP96002/d, rev. 2 1-15 timer/event counter table 1-7 timer/event counters signal name type state during reset signal description tio0 tio1 input or output input timer/event counter ?he bidirectional tio signal connects to the on-chip timer/event counter. when tio is used as an input, the module is functioning as an external event counter or is measuring external pulse width/signal period. when tio is used as an output, the module is functioning as a timer, and tio becomes the timer pulse. when the tio pin is not used by the timer module, it can be used as a general purpose input/output (gpio) pin. the timer can use internal or external clocking and can interrupt the processor after a number of events specified by a user program, or it can signal an external device after counting internal events. the timer can also be used to trigger dma transfers after a specified number of events (clocks) occurs. when the timer is disabled, the tio pin becomes tri-stated. to prevent undesired spikes from occurring, the tio pin should be pulled up or down when it is not in use. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions once port 1-16 DSP96002/d, rev. 2 motorola once port table 1-8 on-chip emulation port (once) signals signal name signal type state during reset signal description dsi/os0 output low output debug serial input/chip status 0 serial data or commands are provided to the once controller through the dsi/os0 signal when it is an input. the data received on the dsi signal will be recognized only when the dsp has entered the debug mode of operation. data is latched on the falling edge of the dsck serial clock. data is always shifted into the once serial port most significant bit (msb) first. when the dsi/os0 signal is an output, it works in conjunction with the os1 signal to provide chip status information. the dsi/os0 signal is an output when the processor is not in debug mode. when switching from output to input, the signal is tri-stated. note: if the once interface is in use, an external pull-down resistor should be attached to this pin. if the once interface is not in use, the resistor is not required. dsck/ os1 output low output debug serial clock/chip status 1 the dsck/os1 signal supplies the serial clock to the once when it is an input. the serial clock provides pulses required to shift data into and out of the once serial port. (data is clocked into the once on the falling edge and is clocked out of the once serial port on the rising edge.) the debug serial clock frequency must be no greater than 1 / 8 of the processor clock frequency. when switching from input to output, the signal is tri-stated. when it is an output, this signal works with the os0 signal to provide information about the chip status. the dsck/os1 signal is an output when the chip is not in debug mode. note: if the once interface is in use, an external pull-down resistor should be attached to this pin. if the once interface is not in use, the resistor is not required. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions once port motorola DSP96002/d, rev. 2 1-17 dso output output, pulled high debug serial output data contained in one of the once controller registers is provided through the dso output signal, as specified by the last command received from the external command controller. data is always shifted out the once serial port msb first. data is clocked out of the once serial port on the rising edge of dsck. the dso signal also provides acknowledge pulses to the external command controller. when the chip enters the debug mode, the dso signal will be pulsed low to indicate (acknowledge) that the once is waiting for commands. after the once receives a read command, the dso signal will be pulsed low to indicate that the requested data is available and the once serial port is ready to receive clocks in order to deliver the data. after the once receives a write command, the dso signal will be pulsed low to indicate that the once serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. dr input input debug request the debug request input (dr ) allows the user to enter the debug mode of operation from the external command controller. when dr is asserted, it causes the dsp to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the dsi line. while in debug mode, the dr signal lets the user reset the once controller by asserting it and deasserting it after receiving acknowledge. it may be necessary to reset the once controller in cases where synchronization between the once controller and external circuitry is lost. dr must be deasserted after the once responds with an acknowledge on the dso signal and before sending the first once command. asserting dr will cause the chip to exit the stop or wait state. having dr asserted during the deassertion of reset will cause the dsp to enter debug mode. note: if the once interface is not in use, attach an external pull-up resistor to the dr input. table 1-8 on-chip emulation port (once) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions once port 1-18 DSP96002/d, rev. 2 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola DSP96002/d, rev. 2 2-1 section 2 specifications introduction the digital signal processor (dsp) is fabricated using high-density complementary metal oxide semiconductor (cmos) with transistor-transistor- logic (ttl) compatible inputs and outputs. this section covers the maximum ratings, thermal characteristics, and electrical characteristics of the DSP96002. note: reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). maximum ratings note: in the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite direction. therefore, a ?aximum?value for a specification will never occur in the same device that has a ?inimum?value for another specification; adding a maximum to a minimum represents a condition that can never exist. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications thermal characteristics 2-2 DSP96002/d, rev. 2 motorola thermal characteristics table 2-1 maximum electrical ratings rating symbol value unit supply voltage v cc ?.3 to +7.0 v all input voltages v in gnd ?0.5 to v cc + 0.5 v current drain per pin excluding v cc and v ss 1 i10ma operating temperature range t j ?0 to +100 c storage temperature t stg ?5 to +150 c note: gnd = 0 vdc table 2-2 thermal characteristics characteristic symbol pga value cqfp value unit junction to ambient 1 r q ja or q ja 22 31 c/w junction to case 2 r q jc or q jc 5.7 1.6 c/w thermal characterization parameter y jt 5.2 1.0 c/w note: 1. junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per semi g38-87 in natural convection. semi is semiconductor equipment and materials international, 805 east middlefield road, mountain view, ca 94043, (415) 964-5111. 2. junction-to-case thermal resistance is based on measurements using a cold plate per semi g30-88 with the exception that the cold plate temperature is used for the case temperature. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications dc electrical characteristics motorola DSP96002/d, rev. 2 2-3 dc electrical characteristics table 2-3 dc electrical characteristics characteristic 1 symbol min typical max unit supply voltage, + 10% at 33.3 mhz + 5% at 40 mhz +5% at 60 mhz v cc 4.5 4.75 4.75 5.0 5.0 5.0 5.5 5.25 5.25 v v v input high voltage except clk, reset moda, modb,modc v ih 2.0 v cc v input low voltage except clk, moda, modb, modc v il ?.5 0.8 v input high voltage clk v ihc 4.0 v cc v input low voltage clk v ilc ?.5 0.6 v input high voltage reset v ihr 2.5 v cc v input high voltage moda, modb, modc v ihm 3.5 v cc v input low voltage moda, modb, modc v ilm ?.5 2.0 v input leakage current ? in ?0 10 m a tri-state (off- state) input current @2.4 v/0.5 v i tsi ?0 10 m a output high voltage i oh = ?0 m a v ohc v cc ? 0.1 v output high voltage i oh = ?.4 ma v oh 2.4 v output low voltage i ol = 10 m a v olc 0.1 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications dc electrical characteristics 2-4 DSP96002/d, rev. 2 motorola output low voltage i ol = 3.2 ma v ol 0.4 v power dissipation f = 33.3 mhz 2,3 f = 40 mhz 2,3 f = 60 mhz 2,3 p d 1.0 1.25 1.75 w total supply current 5 v, 33.3 mhz wait mode 2,3 stop mode 2,3 5 v, 40 mhz wait mode 2,3 stop mode 2,3 5 v, 60 mhz wait mode 2,3 stop mode 2,3 i dd i ddw i dds i dd i ddw i dds i dd i ddw i dds 200 18 80 250 20 100 350 22 300 350 26 400 400 34 500 500 40 600 ma ma m a ma ma m a ma ma m a input capacitance 4 ? in ?0 pf note: 1. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 2. p d is measured for v il 0.2 v, v ih 3 v cc ? 0.2v. with no dc loads. clk is driven by a 50% duty- cycle oscillator. 3. in order to obtain these results all inputs must be terminated (i.e., not allowed to float). 4. input capacitance is not tested in production. table 2-3 dc electrical characteristics (continued) characteristic 1 symbol min typical max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-5 ac electrical characteristics the timing waveforms shown in this section are tested with the following values: ac timing specifications that are referenced to a device input signal are measured in production with respect to the v ih /v il levels of the respective input signal? transition. ac timing specifications that are referenced to a device? output levels are measured with the production test machine v ol and v oh reference levels set at 0.8 v and 2.0 v, respectively. for load capacitances greater than 50pf, the drive capability of the output pins derates linearly at 1.5 ns per 20 pf of additional capacitance from 50 pf to 200 pf of loading, and at 2 ns per 20 pf of additional capacitance for loads greater than 200 pf. v il maximum of 0.5 v v ih minimum of 2.4 v for all pins 1 note: 1. clk, reset , moda, modb, and modc are tested using the input levels described in dc electrical characteristics on page 2-3. figure 2-1 signal measurement reference v ih v il fall time rise time pulse width low high 10% 50% 90% input signal note: 1. the midpoint is v il + (v ih ?v il )/2 midpoint 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-6 DSP96002/d, rev. 2 motorola clock operation the DSP96002 system clock is derived from a crystal or an external system clock signal. the clock input is an active high input, high frequency processor clock. the frequency is twice the instruction rate. an internal phase generator divides clk into four phases (t 0 , t 1 , t 2 and t 3 ), which is the basic instruction execution cycle. additional t w phases are optionally generated to insert wait states (ws) into instruction execution. a wait state is formed by pairing a t 2 and t w phase. clk should be continuous with a 46?4% duty cycle. table 2-4 clock operation no. 1 characteristic 2 symb. 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max instruction cycle time = 2t c = 4t instruction cycle time = 2t c = 4t i cyc 60 50 33.3 ns wait state = t c = 2t wait state = t c = 2t ws 30 25 16.7 ns 71 clk cycle time clk cycle time t c 30 25 16.7 ns 72 clk rise time 4 ??ns 73 clk fall time 4 ??ns 74a clk high t h 14 16 11.5 13.5 7.7 9.5 ns 74b clk low t l 14 16 11.5 13.5 7.7 9.5 ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. 46%?4% duty cycle 4. 46.7%?3.3% duty cycle figure 2-2 clk timing diagram clk v ilc v ihc midpoint 1 74a 71 74b 72 t h t l 73 note: 1. the midpoint is 0.5 (v cc ?gnd). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-7 arbitration bus timing table 2-5 arbitration bus timing no. 1 characteristic 2 33.3 mhz 40 mhz 60 mhz unit min max min max min max 1 clk high to br asserted / deasserted 214212210ns 2bg valid to clk high (setup) 6?? ns 3 clk high to bg invalid (hold) 2?? ns 4 clk high to ba asserted / deasserted 214212210ns 5bb valid to clk high (setup) 6?? ns 6 clk high to bb invalid (hold) 2?? ns 7 clk high to a0?31, s0?1, r/w , bs , tt , and bl active 2102827ns 8 a0?31, s0?1, r/w , bs , and tt tri- state to ba deasserted 0?? ns 9 clk high to a0?31, s0?1, r/w , bs , and ts tri-state 2122102 8ns 9a clk low to ba tri-state 2 12 2 10 2 8 ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-8 DSP96002/d, rev. 2 motorola figure 2-3 bus acquisition timing clk (input) (tri-state) (tri-state) (tri-state) 5 br (output) bg (input) bb (input) ba (output) a0?31, ts r/w , s0?1, bs , tt , bl (output) (output) 2 3 7 4 31 1 41 6 wr write cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-9 figure 2-4 bus release timing clk (input) (tri-state) (tri-state) (tri-state) br (output) bg (input) ba (output) bs (output) a0?31, ts r/w , s0?1 (output) (output) 2 3 8 4 39 1 9a (tri-state) 9 9 9 42 43 (tri-state) 9 42a 43a wr write cycle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-10 DSP96002/d, rev. 2 motorola external bus relative timing table 2-6 external bus relative timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 10 a0?31, s0?1, r/w valid to ts asserted expression: 10 5 16 6 7.5 5 13.5 6 4.0 5 9.5 6 ns 11 a0?31, s0?1, r/w valid to ts deasserted 42 7 33.5 8 25.0 8 ?s 12 ts width asserted 30 9 ?5 9 ?7 9 ?s 12a wr width asserted 27 27 ?2 27 ?5 27 ?s 13 ts deasserted to r/w , a0?31 invalid 6 10 6.5 11 6.5 11 ?s 13a wr deasserted to r/w , a0?31 invalid 6 3.5 2.5 ns 14 ts width deasserted 21 12 ?8 13 ? 613 ?s 14a wr width deasserted 18 15 10 ns 15 ts asserted to d0?31 valid (write cycle) ?0 14 17.5 14 ?5 14 ns 16 d0?31 valid to ts deasserted (write cycle) 12 15 8.5 16 ? 16 ?s 16a d0?31 valid to wr deasserted (write cycle) 12 28 ?0 29 6.5 29 ?s 17 ts deasserted to d0?31 invalid (write cycle) 6 10 6.5 11 6.5 11 ?s 17a wr deasserted to d0?31 invalid (write cycle) 6 3.5 2.5 ns 18 ts asserted to d0?31 active (write cycle) 10 17 ?0 18 7.7 18 ?s 19 ts deasserted to d0?31 tri?tate (write cycle) ?6 19 13.5 19 ?1 19 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-11 19a wr deasserted to d0?31 three-state (write cycle) ?6 19 13.5 19 ?1 19 ns 20 ts deasserted to d0?31 active (write cycle) 35 20 31.5 21 26.5 21 ?s 21 ts asserted to d0?31 valid (read cycle) ?1 22 17.5 23 ?4 23 ns 22 ts deasserted to d0?31 invalid (hold) (read cycle) 0?? ns 23 a0?31, s0?1, r/w valid to d0?31 valid (read cycle) 24 ?2 25 26.5 26 ?1 26 ns table 2-6 external bus relative timing (continued) no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd= 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% and no wait states 4. assuming duty cycle in the range 46%?4% and no wait states 5. t h ? 6. t h 7. (ws + 1)t c + t h ? 8. (ws + 1)t c + t h ?3 9. (ws + 1)t c 10. t l ?8 11. t l ?5 12. t c ?9 13. t c ?7 14. t l + 4 15. (ws)t c + t h ?2 16. (ws)t c + t h ?3 17. t l ?4 18. t l ?1.5 19. t l 20. t c + t l ?9 21. t c + t l ?5 22. (ws + 1)t c ?9 23. (ws + 1)t c ?7.5 24. using t h minimum 25. (ws + 1)t c + t h ?12 26. (ws + 1)t c + t h ?10 27. t c ?3 28. t h ?2 29. t h ?1.5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-12 DSP96002/d, rev. 2 motorola figure 2-5 external bus relative timing (tri-state) (tri-state) r/w (output) ts (output) d0?31 a0?31, s0?1 (output) (see note) 10 22 11 12 18 20 16 15 data out 13 17 19 14 10 21 23 13 data in (tri-state) note: during read-modify-write instructions, a0?31, s0?1 do not change. wr 12a 14a 10 11 16a 17a 19a 13a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-13 external bus synchronous timing table 2-7 external bus synchronous timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 31 clk high to a0?31, s0?1, r/w valid and tt , bs , bl asserted 214212210ns 32 clk high to a0?31, s0?1, r/w invalid 2 1.5 1.5 ns 33 clk high to d0?31 valid (write cycle) 214212210ns 34 clk high to d0?31 invalid (write cycle) 2 1.5 1.5 ns 35 clk high to d0?31 active (write cycle) 2 1.5 1.5 ns 36 clk high to d0?31 three-state (write cycle) ?2?0 8.5ns 37 d0?31 valid to clk low (setup) (read cycle) 0?? ns 38 clk low to d0?31 invalid (hold) (read cycle) 11?? ns 39 clk high to tt , bs , bl deasserted 2 14 2 12 2 10 ns 40 bs , tt width deasserted 25 6 ?1 7 16.5 7 ?s 41 clk low to ts asserted 2 11 1.5 9.5 1.5 8 ns 41a clk high ts tri-state 2 11 1.5 9.5 1.5 8 ns 42 ts hold time from clk low 2 1.5 1.0 ns 42a wr hold time from clk low 1.5 1.5 1.0 ns 43 clk low to ts deasserted 16 13 9 ns 43a clk low to wr deasserted 19 16 13 ns 44 ts deasserted to bs asserted (two successive bus cycles) 7 8 6.5 9 6.5 9 ?s 44a wr deasserted to bs asserted (two successive bus cycles) 6 3.5 3. ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-14 DSP96002/d, rev. 2 motorola 45 bs asserted to ta asserted 5. ?5 10 12.5 11 9.5 11 ns 46 ta valid to clk high (setup) 5. 3?? ns 47 clk high to ta invalid (hold) 8?? ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% and no wait states 4. assuming duty cycle in the range 46%?4% and no wait states 5. timing 45 or timing 46 should be satisfied. 6. t c ? 7. t c ? 8. t l ? 9. t l ? 10. t c ?5 11. t c ?2.5 table 2-7 external bus synchronous timing (continued) no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-15 figure 2-6 external bus synchronous timing?o wait states clk (input) ta (input) d0?31 (output) bs , tt (output) a0?31, d0?31 r/w , s0?1 (output) (input) ts (output) 31 39 40 32 41 45 46 35 37 38 36 34 47 42 44 43 33 wr (output) 41a 42a 43a 44a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-16 DSP96002/d, rev. 2 motorola figure 2-7 external bus synchronous timing?ne wait state clk (input) a0?31, bs , tt r/w , s0?1, (output) (output) 41 31 ta (input) ts (output) 47 46 46 47 39 32 43 44 42 40 wr (output) 41a 43a 42a 44a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-17 figure 2-8 read-modify-write cycle timing?o wait states clk (input) a0?31, s0?1 (output) r/w (output) ts (output) bl (output) bs , tt (output) 31 31 31 39 41 43 44 42 39 39 40 32 39 wr (output) 41a 42a 43a 44a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-18 DSP96002/d, rev. 2 motorola multiplexed bus timing table 2-8 multiplexed bus timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 51 ae asserted to clk low 5 814 6 6.5 11.5 6 5.5 9 6 ns 52 ae asserted to a0?31 valid 2 14 2 12 2 10 ns 53 ae deasserted to a0?31 tri-state 2 12 2 10 1.5 8 ns 54 ae deasserted to a0?31 invalid 2? 1.5 ns 55 ae asserted to clk high 7 012 8 0 9.5 9 07 9 ns 56 ae asserted to a0?31 active 1?? ns 57 clk high to a0?31 active 2 1.5 1.5 ns 61 de asserted to clk low 5 , 10 814 6 6.5 11.5 6 5.5 9 6 ns 62 de asserted to d0?31 valid 14 2 2 12 2 10 ns 63 de deasserted to d0?31 tri-state 2 12 2 10 1.5 8 ns 64 de deasserted to d0?31 invalid 2? 1.5 ns 65 de asserted to clk high 7 , 10 012 8 0 9.5 9 07 9 ns 66 de asserted to d0?31 active 1?? ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% 4. assuming duty cycle in the range 46%?4% 5. t h minimum 6. t h 7. t l minimum 8. t l ? 9. t l ? 10. for host interface data output, only timings 62, 63, 64, and 66 apply. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-19 figure 2-9 address bus enable/disable timing figure 2-10 data bus enable/disable timing 51 56 52 53 54 55 57 54 53 31 clk (input) ae (input) a0?31 (output) 61 66 62 63 64 65 35 64 63 33 clk (input) de (input) d0?31 (output) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-20 DSP96002/d, rev. 2 motorola host timing table 2-9 host timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 101 a2?5, r/w valid to ts asserted (setup) 10?? ns 102 ts deasserted to a2?5, r/w invalid (hold) 0?? ns 103 ts asserted to d0?31 out valid ts asserted to d0?31 out valid 5 18 6 100 16 88 13.5 74 ns ns 104 ts , ha deasserted to d0?31 out invalid (hold) 2?? ns 105 ts , ha asserted to d0?31 out active 3?? ns 106 ts , ha deasserted to d0?31 tri-state 18 16 14 ns 107 a2?5, r/w valid to d0?31 valid to d0?31 out valid a2?5, r/w valid to d0?31 valid to d0?31 out valid 5 30 6 100 25 88 20 74 ns ns 108 hs , ha asserted to d0?31 out valid (access time) hs , ha asserted to d0?31 out valid 5 ?1 6 ?0?7ns 109 d0?31 in valid to ts , ha deasserted (setup) 8?? ns 110 ts , ha deasserted to d0?31 in invalid (hold) 5? 3.5 ns 111 ts width asserted 5 16?4?2?s 112 ts width deasserted between consecutive tx writes 8 ts , ha width deasserted (others) 11 79 12 64.5 10 51.5 9 ns ns 113 hs asserted to ts deasserted 24 21 17 ns 114 hs hold time after ts deasserted 0?? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-21 115 hs , ha deasserted to ts asserted (setup) 1?? ns 118 ha width asserted (dma mode) 24 21 18 ns 120 clk low to hr asserted 14 12 10 ns 121 ts , ha asserted to hr deasserted 30 25 21 ns 122 clk low to hr asserted after ts deassertion 12 60?0?0?s 123 ts , ha deasserted to clk low (setup) 14 13 30 11 25 9.5 20 ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% 4. assuming duty cycle in the range 46%?4% 5. when reading status (ics register), the status data is guaranteed to be stable. 6. 2t c + 40 7. 2t c + 38 8. assuming both tx and hrx empty 9. 2t c + t l + 5 10. 2t c + t l + 3 11. both ts and ha must be deasserted in case of mixed dma / non-dma accesses (i.e., after any access this recovery time must be respected before a new access.) 12. when ts deassertion was in respect to timing 123 13. 2t c 14. when timing 123 is respected, timing 122 is guaranteed to be respected. timing 123 is not required for correct operation. 15. t c table 2-9 host timing (continued) no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-22 DSP96002/d, rev. 2 motorola figure 2-11 host read cycle timing (non-dma mode) figure 2-12 host write cycle timing (non-dma mode) a2?5 (input) r/w (input) hs (input) ts (input) d0?31 (output) 101 107 111 103 108 106 112 115 104 114 102 105 a2?5 (input) r/w (input) hs (input) ts (input) d0?31 (input) 101 111 113 112 115 110 114 102 109 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-23 figure 2-13 host read cycle timing (dma mode) figure 2-14 host write cycle timing (dma mode) figure 2-15 host interrupt vector register (ivr) read timing (non-dma mode) hr (output) ha (input) d0?31 (output) 105 118 108 121 112 106 104 hr (output) ha (input) d0?31 (input) 118 121 112 110 109 d0?31 (output) 107 102 114 104 106 105 103 111 108 112 115 ts (input) ha (input) r/w (input) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-24 DSP96002/d, rev. 2 motorola figure 2-16 host request timing 123 121 122 120 hr (output) clk (input) ts , ha (input) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-25 once timing table 2-10 once timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 130 dsck low 40 40 40 ns 131 dsck high 40 40 35 ns 132 dsck cycle time 240 200 160 ns 133 dr asserted to dso (ack ) asserted 152 5 126 6 105 6 ?s 134 dsck high to dso valid 51 42 34 ns 135 dsck high to dso invalid 6?? ns 136 dsi valid to dsck low (setup) 17 15 13 ns 137 dsck low to dsi invalid (hold) 6?? ns 138 last dsck low to os0?s1, ack active 74 7 61.5 7 ?0 7 ?s 139 dso (ack ) asserted to first dsck high 8 81 9 67.5 10 ?4 10 ?s 140 dso (ack ) width asserted 40 11 68 12 33.5 13 57 14 27 46 ns 141 dso (ack ) asserted to os0?s1 tri- state ???ns 142 os0?s1 valid to clk high 10 15 ? 16 ? ns 143 clk high to os0?s1 invalid 4?? ns 144 last dsck low of read register to first dsck high of next command 19 222 17 185.5 18 148 18 ?s 145 last dsck low to dso invalid (hold) 6?? ns 146 dsck rise and fall times 60 60 50 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-26 DSP96002/d, rev. 2 motorola note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% 4. assuming duty cycle in the range 46%?4% figure 2-17 once serial clock timing figure 2-18 once acknowledge timing table 2-10 once timing (continued) no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 5. 5t c + 2 6. 5t c + 1 7. 2t c + t l 8. t l maximum. 9. 2t c + t l + 5 10. 2t c + t l + 4 11. t c + t l ?4 12. 2t c + 8 13. t c + t l ?3 14. 2t c + 7 15. t c ?20 16. t c ?17 17. 6t c + t h + 26 18. 6t c + t h + 22 19. t h maximum 131 dsck (input) 130 132 146 146 133 dr (input) dso (output) ack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-27 figure 2-19 once data i/o to status timing figure 2-20 once status to data i/o timing figure 2-21 once clk to status timing dsck (input) 134 138 137 136 135 dso (output) dsi (input) (last) (note 1) (os1) (ack ) (os0) note: tri -state, external pull-down resistor 145 note: tri -state, external pull-down resistor os1 (output) dso (output) os0 (output) (ack ) (note 1) 139 140 134 137 136 141 (dsck input) (dso output) (dsi input) 142 143 clk (input) os0-1 (output) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-28 DSP96002/d, rev. 2 motorola reset, mode select, interrupt timing figure 2-22 once dsck next command after read register timing table 2-11 reset, mode select, interrupt timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 160 reset asserted to d0?31, a0?31, s0?1, r/w , bs , tt , ts , ba three- state ?0 9 ?0 10 ?0ns 161 reset asserted to bl , br , hr deasserted 100 11 ?5 12 ?0ns 162 reset width asserted 5 600 13 500 13 400 13 ?s 163 asynchronous reset deassertion to first external access 300 14 365 15 250 14 305 16 200 14 245 16 ns 164 synchronous reset setup time from reset deassertion to clk high 625 17 520 17 416 17 ns 165 synchronous reset delay from clk high to first external access 7 242 18 254 19 202 18 212 20 162 18 170 ns 166 mode select setup time 50 50 40 ns 167 mode select hold time 0 0? ns 168 edge-triggered interrupt request width 10 10?0 ns 169 delay from irqa , irqb , or irqc assertion to external memory access out valid caused by first interrupt instruction execution 6 284 21 236.5 21 189 21 ?s dsck (input) (read register) (next command) 144 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-29 170 delay from a0?31, s0?1, r/w , bs , and tt valid caused by first interrupt instruction execution to irqa , irqb , irqc deassertion 8 ?0 22 ?5 23 ?0 23 ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% and no wait states 4. assuming duty cycle in the range 46%?4%% and no wait states 5. assuming stable clk and v cc 6. assuming a single-cycle move instruction in the first vector location, interrupting a stream of one- word, single-cycle instructions 7. assuming bg asserted and bb deasserted 8. this timing is necessary to prevent multiple interrupt service when the interrupt request is a level- sensitive fast interrupt. to avoid this restriction, edge-triggered mode is recommended when using fast interrupts and long interrupts are recommended when using level-sensitive mode table 2-11 reset, mode select, interrupt timing (continued) no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 9. t c + 40 10. t c + 35 11. 2t c + 40 12. 2t c + 35 13. 20t c 14. 10t c 15. 11t c + 35 16. 11t c + 30 17. t c ?5 18. 8t c + 2 19. 8t c + 14 20. 8t c + 12 21. 9t c + tl 22. (ws + 2)t c ?30 23. (ws + 2)t c ?25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-30 DSP96002/d, rev. 2 motorola figure 2-23 reset entry timing figure 2-24 asynchronous reset exit timing figure 2-25 synchronous reset exit timing d0?31, a0?31, s0?1, r/w , bs , tt , ts , ba reset (input) bl , br , hr (output) 162 161 160 v ihr (output) reset (input) bus signals (output) v ihr first fetch 163 clk (input) reset (input) bus signals (output) first fetch v ihr 164 165 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-31 figure 2-26 operating mode select timing figure 2-27 external edge-triggered interrupt timing figure 2-28 external level-sensitive interrupt timing reset (input) moda, modb, modc (input) v ihr v ih v ihm v ilm v il irqa , irqb , irqc v ih 166 167 162 note: reset, mode select, interrupt figure 5 irqa , irqb , irqc (input) a0?31, s0?1, r/w , bs , (output) tt first interrupt instruction execution 168 169 irqa , irqb , irqc (input) a0?31, s0?1, r/w , bs , (output) tt first interrupt instruction execution 169 170 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-32 DSP96002/d, rev. 2 motorola wait, stop, dma request timing table 2-12 wait, stop, dma request timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 180 irqa , irqb , irqc asserted to clk low (setup time for synchronous recovery from wait state) 12 30 10 25 8 17 ns 181 clk low to external memory access valid (first interrupt instruction fetch after synchronous recovery from wait state) 5 406 7 420 8 338.5 7 350.5 9 271 7 281 9 ns 182 irqa , irqb , irqc width asserted (recovery from wait state) 35 10 ?0 10 ?0 10 ?s 183 irqa , irqb , irqc asserted to external memory access valid (first interrupt instruction fetch after asynchronous recovery from wait state) 5 406 7 466 11 338.5 7 388.5 12 271 7 311 ns 184 irqa asserted to clk low (setup time for synchronous recovery from stop state) 830 13 725 13 5.5 20 13 ns 185 clk low to external memory access valid (first instruction fetch after synchronous recovery from stop state) 5 376 14 390 15 313.5 14 325.5 16 251 14 261 ns 186 irqa width asserted (recovery from stop state) 35 22 ?0 22 ?5 22 ?s 187 irqa asserted to external memory access valid (first instruction fetch after asynchronous recovery from stop state) 5 ) 376 14 436 17 313.5 14 363.5 18 251 14 291 ns 188 dr asserted to clk low (setup time for synchronous recovery from wait or stop state) 830 13 725 13 5.5 20 13 ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-33 189 clk low to dso (ack ) valid (enter debug mode) after synchronous recovery from stop state after synchronous recovery from wait state 540 19 510 20 450 19 425 20 305 19 290 20 ns ns 190 dr asserted to dso (ack ) valid (enter debug mode) after asynchronous recovery from stop state after asynchronous recovery from wait state 540 19 510 20 450 19 425 20 305 19 290 20 ns ns 191 dma request asserted to clk low (setup) 6 6?? ns 192 clk low to dma request invalid (hold) 6 2? 1.5 ns 193 clk low to external dma access valid 76 21 63.5 21 ?0 21 ?s 194 dr assertion width to recover from wait/stop to recover from wait/stop and enter debug mode 35 22 420 25 300 23 29 24 350 25 250 23 23 24 235 25 200 23 ns ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, gnd = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, gnd = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% and no wait states. 4. assuming duty cycle in the range 46%?4%% and no wait states. 5. assuming bus ownership. 6. irq pin internally defined as dma request. table 2-12 wait, stop, dma request timing (continued) no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 7. 13tc + tl + 2 8. 13tc + tl + 14 9. 13tc + tl + 12 10. tc + 5 11. 14tc + tl + 30 12. 14tc + tl + 25 13. tc 14. 12tc + tl + 2 15. 12tc + tl + 14 16. 12tc + tl + 12 17. 13tc + tl + 30 18. 13tc + tl + 25 19. 18tc 20. 17tc 21. 2tc + tl + 2 22. tc + 5 23. 10tc 24. tc + 4 25. 14tc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-34 DSP96002/d, rev. 2 motorola figure 2-29 recovery from wait state using synchronous interrupt timing figure 2-30 recovery from wait state using asynchronous interrupt timing figure 2-31 recovery from stop state using synchronous interrupt timing irqa , irqb , irqc (input) a0?31, s0?1, r/w , bs , (output) tt first interrupt instruction fetch clk (input) 180 181 irqa , irqb , irqc (input) first interrupt instruction fetch a0?31, s0?1, r/w , bs , (output) tt 183 182 clk (input) first instruction fetch a0?31, s0?1, r/w , bs , (output) tt irqa (input) 185 184 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-35 figure 2-32 recovery from stop state using asynchronous interrupt timing figure 2-33 recovery from wait/stop state using synchronous dr timing figure 2-34 recovery from wait/stop state using asynchronous dr timing first instruction fetch a0?31, s0?1, r/w , bs , (output) tt irqa (input) 186 187 clk (input) dr (input) dso (output) ack 189 188 194 dr (input) dso (output) ack 194 190 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-36 DSP96002/d, rev. 2 motorola timer/event counter figure 2-35 external dma request timing table 2-13 timer timing no. 1 characteristic 2 33.3 mhz 3 40 mhz 4 60 mhz 4 unit min max min max min max 260 tio low 2t c ?t c ?t c ?s 261 tio high 2t c ?t c ?t c ?s 262 ckout to tio (output) assertion 2 18 2 15 2 12 ns 263 ckout to tio (output) deassertion 2 18 2 15 2 12 ns note: 1. the numbers in this column are shown as circled numbers in the following figures. 2. dc electrical characteristics: at 33.3 mhz: v cc = 5.0 v 10%, v ss = 0 v dc, t j = ?0 c to 100 c at 40 or 60 mhz: v cc = 5.0 v 5%, v ss = 0 v dc, t j = ?0 c to 100 c 3. assuming duty cycle in the range 46.7%?3.3% and no wait states. 4. assuming duty cycle in the range 46%?4%% and no wait states. irqa , irqb , irqc (input) clk (input) a0?31, s0?1, r/w , bs , (output) tt dma access 193 192 191 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics motorola DSP96002/d, rev. 2 2-37 figure 2-36 tio timer event input restrictions figure 2-37 external pulse generation 260 261 tio ckout tio (output) 262 263 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications ac electrical characteristics 2-38 DSP96002/d, rev. 2 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola DSP96002/d, rev. 2 3-1 section 3 packaging this section contains package and pin-out information for the DSP96002. there are two package options: 223-pin pin grid array (pga) or 240-pin ceramic quad flat pack (cqfp). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package 3-2 DSP96002/d, rev. 2 motorola pga package figure 3-1 top view of the DSP96002 223-pin pga package 123456789101112131415161718 a ba23 ba27 ba29 ba31 irqa abb abr tio0 ar/w as0 ats aae aa02 aa04 aa07 aa10 aa13 aa16 a b ba20 ba25 ba28 ba30 irqb abg aba btt as1 abs aa00 aa03 aa06 aa09 aa11 aa14 aa18 aa20 b c ba17 ba21 ba26 gnd n irqc res abl at t awr aa01 aa05 aa08 aa12 aa15 aa17 aa19 aa21 aa23 c d ba15 ba18 ba24 gnd n gnd n gnd n v ccn v ccn v ccq gnd q v ccn gnd n gnd n gnd n aa22 aa25 aa26 d e ba13 ba16 ba22 gnd n gnd n aa24 aa28 aa29 e f ba12 ba14 ba19 gnd n gnd n aa27 aa30 ad31 f g ba09 ba10 v ccn v ccn DSP96002 gnd n aa31 ad30 ad29 g h ba08 clk ba11 v ccq 223 pin v ccn ad28 ad27 ad26 h j at a bt a ba07 gnd q pga gnd q ad24 ad25 ad23 j k ba04 ba05 ba06 v ccn top view gnd q ad20 ad21 ad22 k l ba03 ba01 ba02 v ccn v ccq ad16 ad18 ad19 l m ba00 bs1 bs0 gnd n v ccn v ccn ade ad17 m n bae tio1 bwr gnd n gnd n ad11 ad14 ad15 n p br/w bts bbl gnd n gnd n ad07 ad12 ad13 p r bbs bbr bbb gnd n gnd n gnd n v ccn gnd q v ccq v ccq v ccn gnd n gnd n gnd n gnd n ad05 ad09 ad10 r t bbg bba ahr dr ahs bd31 gnd n bd26 bd22 bd17 bd14 bd11 bd07 bd04 bd01 ad02 ad06 ad08 t u bhr dsck nc(1) aha bde bd29 bd27 bd24 bd21 bd18 bd15 bd12 bd09 bd06 bd03 bd00 ad03 ad04 u v dso dsi bha bhs bd30 bd28 bd25 bd23 bd20 bd19 bd16 bd13 bd10 bd08 bd05 bd02 ad00 ad01 v 123456789101112131415161718 top view f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package motorola DSP96002/d, rev. 2 3-3 figure 3-2 bottom view of the DSP96002 223-pin pga package 123456789101112131415161718 v dso dsi bha bhs bd30 bd28 bd25 bd23 bd20 bd19 bd16 bd13 bd10 bd08 bd05 bd02 ad00 ad01 v u bhr dsck nc(1) aha bde bd29 bd27 bd24 bd21 bd18 bd15 bd12 bd09 bd06 bd03 bd00 ad03 ad04 u t bbg bba ahr dr ahs bd31 gnd n bd26 bd22 bd17 bd14 bd11 bd07 bd04 bd01 ad02 ad06 ad08 t r bbs bbr bbb gnd n gnd n gnd n v ccn gnd q v ccq v ccq v ccn gnd n gnd n gnd n gnd n ad05 ad09 ad10 r p br/w bts bbl gnd n gnd n ad07 ad12 ad13 p n bae tio1 bwr gnd n gnd n ad11 ad14 ad15 n m ba00 bs1 bs0 gnd n DSP96002 v ccn v ccn ade ad17 m l ba03 ba01 ba02 v ccn 223 pins v ccq ad16 ad18 ad19 l k ba04 ba05 ba06 v ccn pga gnd q ad20 ad21 ad22 k j at a bt a ba07 gnd q bottom view gnd q ad24 ad25 ad23 j h ba08 clk ba11 v ccq v ccn ad28 ad27 ad26 h g ba09 ba10 v ccn v ccn gnd n aa31 ad30 ad29 g f ba12 ba14 ba19 gnd n gnd n aa27 aa30 ad31 f e ba13 ba16 ba22 gnd n gnd n aa24 aa28 aa29 e d ba15 ba18 ba24 gnd n gnd n gnd n v ccn v ccn v ccq gnd q v ccn gnd n gnd n gnd n aa22 aa25 aa26 d c ba17 ba21 ba26 gndn irqc res abl at t awr aa01 aa05 aa08 aa12 aa15 aa17 aa19 aa21 aa23 c b ba20 ba25 ba28 ba30 irqb abg aba btt as1 abs aa00 aa03 aa06 aa09 aa11 aa14 aa18 aa20 b a ba23 ba27 ba29 ba31 irqa abb abr tio0 ar/w as0 ats aae aa02 aa04 aa07 aa10 aa13 aa16 a 123456789101112131415161718 bottom view f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package 3-4 DSP96002/d, rev. 2 motorola table 3-1 DSP96002 pin list, 223-pin pga package pin number signal type signal name a1 input/output ba23 a2 input/output ba27 a3 input/output ba29 a4 input/output ba31 a5 input moda/irqa a6 input abb a7 output abr a8 input/output tio0 a9 input/output ar/w a10 output as0 a11 input/output ats a12 input aae a13 input/output aa02 a14 input/output aa04 a15 input/output aa07 a16 input/output aa10 a17 input/output aa13 a18 input/output aa16 b1 input/output ba20 b2 input/output ba25 b3 input/output ba28 b4 input/output ba30 b5 input modb/irqb b6 input abg b7 output aba b8 output btt b9 output as1 b10 output abs b11 input/output aa00 b12 input/output aa03 b13 input/output aa06 b14 input/output aa09 b15 input/output aa11 b16 input/output aa14 b17 input/output aa18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package motorola DSP96002/d, rev. 2 3-5 b18 input/output aa20 c1 input/output ba17 c2 input/output ba21 c3 input/output ba26 c4 input gnd n c5 input modc/irqc c6 input reset c7 output abl c8 output att c9 output awr c10 input/output aa01 c11 input/output aa05 c12 input/output aa08 c13 input/output aa12 c14 input/output aa15 c15 input/output aa17 c16 input/output aa19 c17 input/output aa21 c18 input/output aa23 d1 input/output ba15 d2 input/output ba18 d3 input/output ba24 d5 input gnd n d6 input gnd n d7 input gnd n d8 input v ccn d9 input v ccn d10 input v ccq d11 input gnd n d12 input v ccn d13 input gnd n d14 input gnd n d15 input gnd n d16 input/output aa22 d17 input/output aa25 d18 input/output aa26 table 3-1 DSP96002 pin list, 223-pin pga package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package 3-6 DSP96002/d, rev. 2 motorola e1 input/output ba13 e2 input/output ba16 e3 input/output ba22 e4 input gnd n e15 input gnd n e16 input/output aa24 e17 input/output aa28 e18 input/output aa29 f1 input/output ba12 f2 input/output ba14 f3 input/output ba19 f4 input gnd n f15 input gnd n f16 input/output aa27 f17 input/output aa30 f18 input/output ad31 g1 input/output ba09 g2 input/output ba10 g3 input v ccn g4 input v ccn g15 input gnd n g16 input/output aa31 g17 input/output ad30 g18 input/output ad29 h1 input/output ba08 h2 input clk h3 input/output ba11 h4 input v ccq h15 input v ccn h16 input/output ad28 h17 input/output ad27 h18 input/output ad26 j1 input ata j2 input bta j3 input/output ba07 j4 input gnd q table 3-1 DSP96002 pin list, 223-pin pga package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package motorola DSP96002/d, rev. 2 3-7 j15 input gnd q j16 input/output ad24 j17 input/output ad25 j18 input/output ad23 k1 input/output ba04 k2 input/output ba05 k3 input/output ba06 k4 input v ccn k15 input gnd q k16 input/output ad20 k17 input/output ad21 k18 input/output ad22 l1 input/output ba03 l2 input/output ba01 l3 input/output ba02 l4 input v ccn l15 input v ccq l16 input/output ad16 l17 input/output ad18 l18 input/output ad19 m1 input/output ba00 m2 output bs1 m3 output bs0 m4 input gnd n m15 input v ccn m16 input v ccn m17 input ade m18 input/output ad17 n1 input bae n2 output tio1 n3 input/output bwr n4 input gnd n n15 input gnd n n16 input/output ad11 n17 input/output ad14 n18 input/output ad15 table 3-1 DSP96002 pin list, 223-pin pga package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package 3-8 DSP96002/d, rev. 2 motorola p1 input/output br/w p2 input/output bts p3 output bbl p4 input gnd n p15 input gnd n p16 input/output ad07 p17 input/output ad12 p18 input/output ad13 r1 output bbs r2 output bbr r3 input bbb r4 input gnd n r5 input gnd n r6 input gnd n r7 input v ccn r8 input gnd q r9 input v ccq r10 input v ccq r11 input v ccn r12 input gnd n r13 input gnd n r14 input gnd n r15 input gnd n r16 input/output ad05 r17 input/output ad09 r18 input/output ad10 t1 input bbg t2 output bba t3 output ahr t4 input dr t5 input ahs t6 input/output bd31 t7 input gnd n t8 input/output bd26 t9 input/output bd22 t10 input/output bd17 table 3-1 DSP96002 pin list, 223-pin pga package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package motorola DSP96002/d, rev. 2 3-9 t11 input/output bd14 t12 input/output bd11 t13 input/output bd07 t14 input/output bd04 t15 input/output bd01 t16 input/output ad02 t17 input/output ad06 t18 input/output ad08 u1 output bhr u2 input/output dsck/os1 u3 n/a nc 1 u4 input aha u5 input bde u6 input/output bd29 u7 input/output bd27 u8 input/output bd24 u9 input/output bd21 u10 input/output bd18 u11 input/output bd15 u12 input/output bd12 u13 input/output bd09 u14 input/output bd06 u15 input/output bd03 u16 input/output bd00 u17 input/output ad03 u18 input/output ad04 v1 output dso v2 input/output dsi/os0 v3 input bha v4 input bhs v5 input/output bd30 v6 input/output bd28 v7 input/output bd25 v8 input/output bd23 table 3-1 DSP96002 pin list, 223-pin pga package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pga package 3-10 DSP96002/d, rev. 2 motorola v9 input/output bd20 v10 input/output bd19 v11 input/output bd16 v12 input/output bd13 v13 input/output bd10 v14 input/output bd08 v15 input/output bd05 v16 input/output bd02 v17 input/output ad00 v18 input/output ad01 figure 3-3 DSP96002 mechanical information, 223-pin pga package table 3-1 DSP96002 pin list, 223-pin pga package (continued) pin number signal type signal name case 860c-02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. dim a min max 1.840 1.880 inches b 1.840 1.880 c 0.120 0.150 d 0.017 0.020 g 0.100 bsc h l 0.170 0.190 f 0.030 m te ss 0.010 m t 0.050 bsc b a -f- -e- a b c d e f g h j k l m n p r t u v 18 15 10 6 1 1716 14131211 987 5432 h g g h c 223x d l -t- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package motorola DSP96002/d, rev. 2 3-11 cqfp package figure 3-4 top view of the DSP96002 240-pin cqfp package orientation mark 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 nc nc nc ba28 ba29 ba30 ba31 modc modb moda res abg abb abr aba abl gnd n tio0 v ccn btt att arw awr gnd n as1 as0 ats abs aae aa00 aa01 aa02 aa03 gnd n aa04 aa05 aa06 aa07 gnd q v ccq v ccn aa08 aa09 aa10 aa11 gnd n aa12 aa13 aa14 aa15 aa16 aa17 aa18 aa19 gnd n aa20 aa21 nc nc nc 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 nc nc nc bba gndn bhr ahr dso dsck dsi dr nc bha aha bhs ahs bde bd31 bd30 bd29 bd28 gnd n bd27 bd26 bd25 bd24 v ccn bd23 bd22 bd21 bd20 gnd n bd19 bd18 bd17 bd16 v ccq gnd q bd15 bd14 bd13 bd12 gnd n bd11 bd10 bd09 bd08 v ccn bd07 bd06 bd05 bd04 gnd n bd03 bd02 bd01 bd00 nc nc nc 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 nc nc nc gnd n ba27 ba26 ba25 ba24 v ccn ba23 ba22 ba21 ba20 gnd n ba19 ba18 ba17 ba16 ba15 ba14 ba13 ba12 gnd n ba11 ba10 ba09 ba08 v ccq clk gnd q v ccn ba07 bta ata ba06 ba05 ba04 gnd n ba03 ba02 ba01 ba00 bae bs1 bs0 brw tio1 gnd n bwr bts bbs v ccn bbl bbr bbg bbb nc nc nc nc nc nc nc aa22 aa23 v ccn aa24 aa25 aa26 aa27 gnd n aa28 aa29 aa30 aa31 ad31 ad30 ad29 ad28 gnd n ad27 ad26 ad25 ad24 v ccn ad23 ad22 ad21 ad20 gnd n ad19 ad18 ad17 ad16 v ccq gnd q ad15 /ade ad14 ad13 ad12 gnd n ad11 ad10 ad09 ad08 v ccn ad07 ad06 ad05 ad04 gnd n ad03 ad02 ad01 ad00 nc nc nc nc (top view) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package 3-12 DSP96002/d, rev. 2 motorola figure 3-5 bottom view of the DSP96002 240-pin cqfp package orientation mark 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 nc nc nc nc bbb bbg bbr bbl v ccn bbs bts bwr gnd n tio1 brw bs0 bs1 bae ba00 ba01 ba02 ba03 gnd n ba04 ba05 ba06 ata bta ba07 v ccn gnd q clk ba08 ba09 ba10 ba11 gnd n ba12 ba13 ba14 ba15 ba16 ba17 ba18 ba19 gnd n ba20 ba21 ba22 ba23 v ccn ba24 ba25 ba26 ba27 gnd n nc nc nc nc nc nc ba28 ba29 ba30 ba31 modc modb moda res abg abb abr aba abl gnd n tio0 v ccn btt att arw awr gnd n as1 as0 ats abs aae aa00 aa01 aa02 aa03 gnd n aa04 aa05 aa06 aa07 gnd q v ccq v ccn aa08 aa09 aa10 aa11 gnd n aa12 aa13 aa14 aa15 aa16 aa17 aa18 aa19 gnd n aa20 aa21 nc nc nc nc nc nc bba gnd n bhr ahr dso dsck dsi dr nc bha aha bhs ahs bde bd31 bd30 bd29 bd28 gnd n bd27 bd26 bd25 bd24 v ccn bd23 bd22 bd21 bd20 gnd n bd19 bd18 bd17 bd16 v ccq gnd q bd15 bd14 bd13 bd12 gnd n bd11 bd10 bd09 bd08 v ccn bd07 bd06 bd05 bd04 gnd n bd03 bd02 bd01 bd00 nc nc nc 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 nc nc nc nc ad00 ad01 ad02 ad03 gnd n ad04 ad05 ad06 ad07 v ccn ad08 ad09 ad10 ad11 gnd n ad12 ad13 ad14 /ade ad15 gnd q v ccq ad16 ad17 ad18 ad19 gnd n ad20 ad21 ad22 ad23 v ccn ad24 ad25 ad26 ad27 gnd n ad28 ad29 ad30 ad31 aa31 aa30 aa29 aa28 gnd n aa27 aa26 aa25 aa24 v ccn aa23 aa22 nc nc nc v ccq 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 (on top side) (bottom view) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package motorola DSP96002/d, rev. 2 3-13 table 3-2 DSP96002 pin list, 240-pin cqfp package pin number signal type signal name 1 n/a nc 2 n/a nc 3 n/a nc 4 input/output ba28 5 input/output ba29 6 input/output ba30 7 input/output ba31 8 input irqc /modc 9 input irqb /modb 10 input irqa /moda 11 input reset 12 input abg 13 input abb 14 output abr 15 output aba 16 output abl 17 input gnd n 18 input/output tio0 19 input v ccn 20 output btt 21 output att 22 output ar/w 23 output awr 24 input gnd n 25 output as1 26 output as0 27 input/output ats 28 output abs 29 input aae 30 input/output aa00 31 input/output aa01 32 input/output aa02 33 input/output aa03 34 input gnd n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package 3-14 DSP96002/d, rev. 2 motorola 35 input/output aa04 36 input/output aa05 37 input/output aa06 38 input/output aa07 39 input gnd q 40 input v ccq 41 input v ccn 42 input/output aa08 43 input/output aa09 44 input/output aa10 45 input/output aa11 46 input gnd n 47 input/output aa12 48 input/output aa13 49 input/output aa14 50 input/output aa15 51 input/output aa16 52 input/output aa17 53 input/output aa18 54 input/output aa19 55 input gnd n 56 input/output aa20 57 input/output aa21 58 n/a nc 59 n/a nc 60 n/a nc 61 n/a nc 62 n/a nc 63 n/a nc 64 input/output aa22 65 input/output aa23 66 input v ccn 67 input/output aa24 68 input/output aa25 69 input/output aa26 table 3-2 DSP96002 pin list, 240-pin cqfp package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package motorola DSP96002/d, rev. 2 3-15 70 input/output aa27 71 input gnd n 72 input/output aa28 73 input/output aa29 74 input/output aa30 75 input/output aa31 76 input/output ad31 77 input/output ad30 78 input/output ad29 79 input/output ad28 80 input gnd n 81 input/output ad27 82 input/output ad26 83 input/output ad25 84 input/output ad24 85 input v ccn 86 input/output ad23 87 input/output ad22 88 input/output ad21 89 input/output ad20 90 input gnd n 91 input/output ad19 92 input/output ad18 93 input/output ad17 94 input/output ad16 95 input v ccq 96 input gnd q 97 input/output ad15 98 input ade 99 input/output ad14 100 input/output ad13 101 input/output ad12 102 input gnd n 103 input/output ad11 table 3-2 DSP96002 pin list, 240-pin cqfp package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package 3-16 DSP96002/d, rev. 2 motorola 104 input/output ad10 105 input/output ad09 106 input/output ad08 107 input v ccn 108 input/output ad07 109 input/output ad06 110 input/output ad05 111 input/output ad04 112 input gnd n 113 input/output ad03 114 input/output ad02 115 input/output ad01 116 input/output ad00 117 n/a nc 118 n/a nc 119 n/a nc 120 n/a nc 121 n/a nc 122 n/a nc 123 n/a nc 124 input/output bd00 125 input/output bd01 126 input/output bd02 127 input/output bd03 128 input gnd n 129 input/output bd04 130 input/output bd05 131 input/output bd06 132 input/output bd07 133 input v ccn 134 input/output bd08 135 input/output bd09 136 input/output bd10 137 input/output bd11 138 input gnd n 139 input/output bd12 table 3-2 DSP96002 pin list, 240-pin cqfp package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package motorola DSP96002/d, rev. 2 3-17 140 input/output bd13 141 input/output bd14 142 input/output bd15 143 input gnd q 144 input v ccq 145 input/output bd16 146 input/output bd17 147 input/output bd18 148 input/output bd19 149 input gnd n 150 input/output bd20 151 input/output bd21 152 input/output bd22 153 input/output bd23 154 input v ccn 155 input/output bd24 156 input/output bd25 157 input/output bd26 158 input/output bd27 159 input gnd n 160 input/output bd28 161 input/output bd29 162 input/output bd30 163 input/output bd31 164 input bde 165 input ahs 166 input bhs 167 input aha 168 input bha 169 n/a nc 170 input dr 171 input/output dsi/os0 172 input/output dsk/os1 173 output dso 174 output ahr 175 output bhr table 3-2 DSP96002 pin list, 240-pin cqfp package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package 3-18 DSP96002/d, rev. 2 motorola 176 input gnd n 177 output bba 178 n/a nc 179 n/a nc 180 n/a nc 181 n/a nc 182 n/a nc 183 n/a nc 184 n/a nc 185 input bbb 186 input bbg 187 output bbr 188 output bbl 189 input v ccn 190 output bbs 191 input/output bts 192 output bwr 193 input gnd n 194 input/output tio1 195 output br/w 196 output bs0 197 output bs1 198 input bae 199 output ba00 200 output ba01 201 output ba02 202 output ba03 203 input gnd n 204 output ba04 205 output ba05 206 output ba06 207 input ata 208 input bta 209 output ba07 210 input v ccn table 3-2 DSP96002 pin list, 240-pin cqfp package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package motorola DSP96002/d, rev. 2 3-19 211 input gnd q 212 input clk 213 input v ccq 214 output ba08 215 output ba09 216 output ba10 217 output ba11 218 input gnd n 219 output ba12 220 output ba13 221 output ba14 222 output ba15 223 output ba16 224 output ba17 225 output ba18 226 output ba19 227 input gnd n 228 output ba20 229 output ba21 230 output ba22 231 output ba23 232 input v ccn 233 output ba24 234 output ba25 235 output ba26 236 output ba27 237 input gnd n 238 n/a nc 239 n/a nc 240 n/a nc table 3-2 DSP96002 pin list, 240-pin cqfp package (continued) pin number signal type signal name f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging cqfp package 3-20 DSP96002/d, rev. 2 motorola figure 3-6 DSP96002 mechanical information, 240-pin cqfp package case 988-01 issue e notes: 1. all dimensions and tolerances conform to asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of leads where they exit the body. 1. 4. datums l, m, and n to be determined at datum plane h. 2. 5. dimensions s and v to be determined at seating plane datum t. 3. 6. dimensions a and b define maximum ceramic body dimensions including glass protrusion and top and bottom mismatch. (ab) q 2 (aa) k r 1 q (r) view ae dim min max millimeters a 30.86 31.75 b 30.86 31.75 c 3.75 4.15 d 0.18 0.30 e 3.10 3.90 f 0.17 0.23 g 0.50 bsc j 0.13 0.175 k 0.45 0.55 p 0.25 bsc r 0.15 bsc s 34.60 bsc u 17.30 bsc v 34.60 bsc w y 17.30 bsc z 0.12 0.13 aa 1.80 ref ab 0.95 ref q 1 2 6 q 2 1 7 0.04 0.24 1 240 180 181 61 120 121 60 a view ac 4 places l-n m 0.20 m h l-n 0.30 m t 4x 6 0 tips s u y l v n b m view ae w c e 0.10 t seating plane t h ad ad x = l, m or n view ac x p g z d f j l-n m 0.08 m t 240 places section ad f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging package and pin-out information motorola DSP96002/d, rev. 2 3-21 package and pin-out information complete mechanical information regarding DSP96002 packaging is available by facsimile through motorola's mfax system. call the following number to obtain information by facsimile: the mfax automated system requests the following information: the receiving facsimile telephone number including area code or country code the caller? personal identification number (pin) note: for first time callers, the system provides instructions for setting up a pin, which requires entry of a name and telephone number. the type of information requested: instructions for using the system a literature order form specific part technical information or data sheets other information described by the system messages a total of three documents may be ordered per call. the mechanical drawings for the 223-pin pga package are referenced as 860c-02. the mechanical drawings for the 240-pin cqfp package are referenced as 988-01. (602) 244-6591 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging package and pin-out information 3-22 DSP96002/d, rev. 2 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola DSP96002/d, rev. 2 4-1 section 4 design considerations thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature ?c r q ja = package junction-to-ambient thermal resistance ?c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to- case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r q ja = package junction-to-ambient thermal resistance ?c/w r q jc = package junction-to-case thermal resistance ?c/w r q ca = package case-to-ambient thermal resistance ?c/w r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. t j t a p d r q ja () + = r q ja r q jc r q ca + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . design considerations thermal design considerations 4-2 DSP96002/d, rev. 2 motorola the thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. again, if the estimations obtained from r q ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: to minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. to define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. if the temperature of the package case (t t ) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (t j e t t )/p d . as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. hence, the new thermal metric, thermal characterization parameter or y jt , has been defined to be (t j e t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface, and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . design considerations electrical design considerations motorola DSP96002/d, rev. 2 4-3 electrical design considerations use the following list of recommendations to assure correct dsp operation: provide a low-impedance path from the board power supply to each v cc pin on the dsp, and from the board ground to each gnd pin. use at least six 0.01?.1 m f bypass capacitors positioned as close as possible to the four sides of the package to connect the v cc power source to gnd. ensure that capacitor leads and associated printed circuit traces that connect to the chip v cc and gnd pins are less than 0.5 per capacitor lead. use at least a four-layer printed circuit board (pcb) with two inner layers for v cc and gnd. because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. this recommendation particularly applies to the address and data buses, as well as the irqa , irqb , irqc , ta , ts , bg , hs , and ha pins. maximum pcb trace lengths on the order of 6" are recommended. consider all device loads, as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v cc and gnd circuits. all inputs must be terminated (i.e., not allowed to float) using cmos levels. take special care to minimize noise levels on the v ccpll and v sspll pins. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . design considerations power consumption considerations 4-4 DSP96002/d, rev. 2 motorola power consumption considerations power dissipation is a key issue in portable dsp applications. some of the factors that affect current consumption are described in this section. most of the current consumed by cmos devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. current consumption is described by the formula: equation 3: where: c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle the maximum internal current (i cci max) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. the typical internal current (i ccityp ) value reflects the average switching of the internal buses on typical operating conditions. for applications that require very low current consumption: minimize the number of pins that are switching. minimize the capacitive load on the pins. connect the unused inputs to pull-up or pull-down resistors. disable unused peripherals. disable unused pin activity. example 4-1 current consumption for an i/o pin loaded with 50 pf capacitance, operating at 5.5 v, and with a 60 mhz clock, toggling at its maximum possible rate (30 mhz), the current consumption is: equation 4: i cvf = i5010 12 5.5 30 10 6 8.25 ma == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . design considerations power-up considerations motorola DSP96002/d, rev. 2 4-5 power-up considerations to power-up the device properly, ensure that the following conditions are met: stable power is applied to the device according to the specifications in table 2-3 (dc electrical characteristics). the external clock oscillator is active and stable. reset is asserted according to the specifications in table 2-7 (reset, stop, mode select, and interrupt timing). care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on table 2-1 (maximum ratings), at all phases of the power- up procedure. this may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip. at the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. this is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . design considerations power-up considerations 4-6 DSP96002/d, rev. 2 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola DSP96002/d, rev. 2 5-1 section 5 ordering information consult a motorola semiconductor sales office or authorized distributor to determine product availability and to place an order. table 5-1 ordering information part supply voltage package type pin count frequency (mhz) order number DSP96002 5 v pin grid array (pga) 223 60 DSP96002rc60 40 DSP96002rc40 33 DSP96002rc33 ceramic quad flat pack (cqfp) 240 60 DSP96002fe60 40 DSP96002fe40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information 5-2 DSP96002/d, rev. 2 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola DSP96002/d, rev. 2 a-1 appendix a bootstrap code for DSP96002 ; bootstrap code for DSP96002 - ? copyright 1988 motorola inc. ; ; host algorithm / and / external bus method. ; ; this is the bootstrap program contained in the DSP96002. this program ; can load the internal program memory from one of 4 external sources. ; the program reads the omr bits ma and mb to decide which external ; source to access. ; if mb:ma = 0x - load from 4,096 consecutive byte-wide p: memory ; locations (starting at p:$ffff0000). ; if mb:ma = 10 - load internal pram thru host interface in port a. ; if mb:ma = 11 - load internal pram thru host interface in port b. boot equ $ffff0000; the location in p: memory ; where the external byte-wide ; eprom is expected to be mapped m_hcra equ $ffffffec; port a host control register m_hsra equ $ffffffed; port a host status register m_hrxa equ $ffffffef; port a host rec. data register m_hcrb equ $ffffffe4; port b host control register m_hsrb equ $ffffffe5; port b host status register m_hrxb equ $ffffffe7; port b host rec. data register org pl:$0; bootstrap code starts at p:$0 start move #boot,r1; r1 = external p: address of ; bootstrap byte-wide rom movei #0,r0 ; r0 = starting p: address of ; internal memory where program ; will begin loading. ; if this program is entered by changing the omr to bootstrap mode, ; make certain that registers m0 and m1 have been set to $ffffffff. ; make sure the appropriate bcr register is set to $xxxxxxfx since ; eproms are slow. ; make sure that the port selection register is set to permit program ; memory accesses thru the required memory expansion port (port a or b). ; ; the first routine will load 4,096 bytes from the external p memory ; space beginning at p:$ffff0000 (bits 7-0). these will be condensed ; into 1,024 32-bit words and stored in contiguous internal pram memory ; locations starting at p:$0. note that the first routine loads data ; starting with the least significant byte of p:$0 first. ; the port selection register is not set by this program. it is set ; by hw reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap code for DSP96002 a-2 DSP96002/d, rev. 2 motorola ; the second routine loads the internal pram using the host ; interface logic. ; if hf1=0, it will load 4,096 bytes from the external host processor. ; these will be condensed into 1,024 32-bit words and stored in ; contiguous internal pram memory locations starting at p:$0. note that ; the routine loads data starting with the least significant byte of ; p:$0 first. ; if hf1=1, it will load 1,024 32-bit words from the external host ; processor. ; if the host processor only wants to load a portion of the p memory, ; and start execution of the loaded program, the host interface ; bootstrap load program routine may be killed by setting hf0 = 0. ; inloop do #1024,_loop1; load 1,024 instruction words ; this is the context switch jset #1,omr,_hostld; perform load from host ; interface if mb=1. ; this is the first routine. it loads from external p: memory. do #4,_loop2; get 4 bytes into d0.l lsr #8,d0; shift previous byte down movem p:(r1)+,d1.l; get byte from ext. p mem. lsl #24,d1; shift into upper byte or d1,d0; concatenate _loop2 jmp <_store; then put the word in p memory ; ; this is the second routine. it loads thru the host interface. _hostld jset #0,omr,_hostb; port a or port b? ; boot thru host interface in port a _hosta bclr #5,x:m_hcra; enable port a host interface move #m_hsra,r2; r2 points to hsra move #m_hrxa,r3; r3 points to hrxa jmp <_hostr; go to host routine ; boot thru host interface in port b _hostb bclr #5,x:m_hcrb; enable port b host interface move #m_hsrb,r2; r2 points to hsrb move #m_hrxb,r3; r3 points to hrxb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap code for DSP96002 motorola DSP96002/d, rev. 2 a-3 ; host load routine _hostr _lbl11 jclr #3,x:(r2),_lbl22; if hf0=1, stop loading data. enddo ; must terminate the do loops jmp <_bootend _lbl22 jclr #0,x:(r2),_lbl11; wait for hrdf to go high ; (meaning data is present). jclr #4,x:(r2),_lbl33; 8-bit source? move x:(r3),d0.l; get 32-bit word from host jmp <_store _lbl33 do #4,_loop4; get 4 bytes into d0.l lsr #8,d0; shift previous byte down _lbl1 jclr #3,x:(r2),_lbl2; if hf0=1, stop loading data. enddo ; must terminate the do loops enddo jmp <_bootend _lbl2 jclr #0,x:(r2),_lbl1; wait for hrdf to go high ; (meaning data is present). move x:(r3),d1.l; get byte from host lsl #24,d1; shift into upper byte or d1,d0; concatenate _loop4 _store movem d0.l,p:(r0)+ ; store 32-bit result in p mem. _loop1 ; and go get another 32-bit word ; this is the exit handler that returns execution to internal pram _bootend andi #$f9,omr ; set the operating mode to 00x ; (and trigger an exit from ; bootstrap mode). andi #$0,ccr; clear ccr as if hw reset. ; also delay needed for ; op. mode change. jmp <$0; start fetching from pram. ; DSP96002 bootstrap program size = 50 words f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap code for DSP96002 a-4 DSP96002/d, rev. 2 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola DSP96002/d, rev. 2 b-1 appendix b x and y memory rom tables table b-1 x memory rom contents (full cycle of cosine values) xr:$00000400= $3f800000 $3f7ffec4 $3f7ffb11 $3f7ff4e6 xr:$00000404= $3f7fec43 $3f7fe129 $3f7fd397 $3f7fc38f xr:$00000408= $3f7fb10f $3f7f9c18 $3f7f84ab $3f7f6ac7 xr:$0000040c= $3f7f4e6d $3f7f2f9d $3f7f0e58 $3f7eea9d xr:$00000410= $3f7ec46d $3f7e9bc9 $3f7e70b0 $3f7e4323 xr:$00000414= $3f7e1324 $3f7de0b1 $3f7dabcc $3f7d7474 xr:$00000418= $3f7d3aac $3f7cfe73 $3f7cbfc9 $3f7c7eb0 xr:$0000041c= $3f7c3b28 $3f7bf531 $3f7baccd $3f7b61fc xr:$00000420= $3f7b14be $3f7ac516 $3f7a7302 $3f7a1e84 xr:$00000424= $3f79c79d $3f796e4e $3f791298 $3f78b47b xr:$00000428= $3f7853f8 $3f77f110 $3f778bc5 $3f772417 xr:$0000042c= $3f76ba07 $3f764d97 $3f75dec6 $3f756d97 xr:$00000430= $3f74fa0b $3f748422 $3f740bdd $3f73913f xr:$00000434= $3f731447 $3f7294f8 $3f721352 $3f718f57 xr:$00000438= $3f710908 $3f708066 $3f6ff573 $3f6f6830 xr:$0000043c= $3f6ed89e $3f6e46be $3f6db293 $3f6d1c1d xr:$00000440= $3f6c835e $3f6be858 $3f6b4b0c $3f6aab7b xr:$00000444= $3f6a09a7 $3f696591 $3f68bf3c $3f6816a8 xr:$00000448= $3f676bd8 $3f66becc $3f660f88 $3f655e0b xr:$0000044c= $3f64aa59 $3f63f473 $3f633c5a $3f628210 xr:$00000450= $3f61c598 $3f6106f2 $3f604621 $3f5f8327 xr:$00000454= $3f5ebe05 $3f5df6be $3f5d2d53 $3f5c61c7 xr:$00000458= $3f5b941a $3f5ac450 $3f59f26a $3f591e6a xr:$0000045c= $3f584853 $3f577026 $3f5695e5 $3f55b993 xr:$00000460= $3f54db31 $3f53fac3 $3f531849 $3f5233c6 xr:$00000464= $3f514d3d $3f5064af $3f4f7a1f $3f4e8d90 xr:$00000468= $3f4d9f02 $3f4cae79 $3f4bbbf8 $3f4ac77f xr:$0000046c= $3f49d112 $3f48d8b3 $3f47de65 $3f46e22a xr:$00000470= $3f45e403 $3f44e3f5 $3f43e200 $3f42de29 xr:$00000474= $3f41d870 $3f40d0da $3f3fc767 $3f3ebc1b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-2 DSP96002/d, rev. 2 motorola xr:$00000478= $3f3daef9 $3f3ca003 $3f3b8f3b $3f3a7ca4 xr:$0000047c= $3f396842 $3f385216 $3f373a23 $3f36206c xr:$00000480= $3f3504f3 $3f33e7bc $3f32c8c9 $3f31a81d xr:$00000484= $3f3085bb $3f2f61a5 $3f2e3bde $3f2d1469 xr:$00000488= $3f2beb4a $3f2ac082 $3f299415 $3f286605 xr:$0000048c= $3f273656 $3f26050a $3f24d225 $3f239da9 xr:$00000490= $3f226799 $3f212ff9 $3f1ff6cb $3f1ebc12 xr:$00000494= $3f1d7fd1 $3f1c420c $3f1b02c6 $3f19c200 xr:$00000498= $3f187fc0 $3f173c07 $3f15f6d9 $3f14b039 xr:$0000049c= $3f13682a $3f121eb0 $3f10d3cd $3f0f8784 xr:$000004a0= $3f0e39da $3f0cead0 $3f0b9a6b $3f0a48ad xr:$000004a4= $3f08f59b $3f07a136 $3f064b82 $3f04f484 xr:$000004a8= $3f039c3d $3f0242b1 $3f00e7e4 $3eff17b2 xr:$000004ac= $3efc5d27 $3ef9a02d $3ef6e0cb $3ef41f07 xr:$000004b0= $3ef15aea $3eee9479 $3eebcbbb $3ee900b7 xr:$000004b4= $3ee63375 $3ee363fa $3ee0924f $3eddbe79 xr:$000004b8= $3edae880 $3ed8106b $3ed53641 $3ed25a09 xr:$000004bc= $3ecf7bca $3ecc9b8b $3ec9b953 $3ec6d529 xr:$000004c0= $3ec3ef15 $3ec1071e $3ebe1d4a $3ebb31a0 xr:$000004c4= $3eb8442a $3eb554ec $3eb263ef $3eaf713a xr:$000004c8= $3eac7cd4 $3ea986c4 $3ea68f12 $3ea395c5 xr:$000004cc= $3ea09ae5 $3e9d9e78 $3e9aa086 $3e97a117 xr:$000004d0= $3e94a031 $3e919ddd $3e8e9a22 $3e8b9507 xr:$000004d4= $3e888e93 $3e8586ce $3e827dc0 $3e7ee6e1 xr:$000004d8= $3e78cfcc $3e72b651 $3e6c9a7f $3e667c66 xr:$000004dc= $3e605c13 $3e5a3997 $3e541501 $3e4dee60 xr:$000004e0= $3e47c5c2 $3e419b37 $3e3b6ecf $3e354098 xr:$000004e4= $3e2f10a2 $3e28defc $3e22abb6 $3e1c76de xr:$000004e8= $3e164083 $3e1008b7 $3e09cf86 $3e039502 xr:$000004ec= $3dfab273 $3dee3876 $3de1bc2e $3dd53db9 xr:$000004f0= $3dc8bd36 $3dbc3ac3 $3dafb680 $3da3308c xr:$000004f4= $3d96a905 $3d8a200a $3d7b2b74 $3d621469 xr:$000004f8= $3d48fb30 $3d2fe007 $3d16c32c $3cfb49ba xr:$000004fc= $3cc90ab0 $3c96c9b6 $3c490e90 $3bc90f88 xr:$00000500= $248d4000 $bbc90f88 $bc490e90 $bc96c9b6 xr:$00000504= $bcc90ab0 $bcfb49ba $bd16c32c $bd2fe007 xr:$00000508= $bd48fb30 $bd621469 $bd7b2b74 $bd8a200a table b-1 x memory rom contents (full cycle of cosine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables motorola DSP96002/d, rev. 2 b-3 xr:$0000050c= $bd96a905 $bda3308c $bdafb680 $bdbc3ac3 xr:$00000510= $bdc8bd36 $bdd53db9 $bde1bc2e $bdee3876 xr:$00000514= $bdfab273 $be039502 $be09cf86 $be1008b7 xr:$00000518= $be164083 $be1c76de $be22abb6 $be28defc xr:$0000051c= $be2f10a2 $be354098 $be3b6ecf $be419b37 xr:$00000520= $be47c5c2 $be4dee60 $be541501 $be5a3997 xr:$00000524= $be605c13 $be667c66 $be6c9a7f $be72b651 xr:$00000528= $be78cfcc $be7ee6e1 $be827dc0 $be8586ce xr:$0000052c= $be888e93 $be8b9507 $be8e9a22 $be919ddd xr:$00000530= $be94a031 $be97a117 $be9aa086 $be9d9e78 xr:$00000534= $bea09ae5 $bea395c5 $bea68f12 $bea986c4 xr:$00000538= $beac7cd4 $beaf713a $beb263ef $beb554ec xr:$0000053c= $beb8442a $bebb31a0 $bebe1d4a $bec1071e xr:$00000540= $bec3ef15 $bec6d529 $bec9b953 $becc9b8b xr:$00000544= $becf7bca $bed25a09 $bed53641 $bed8106b xr:$00000548= $bedae880 $beddbe79 $bee0924f $bee363fa xr:$0000054c= $bee63375 $bee900b7 $beebcbbb $beee9479 xr:$00000550= $bef15aea $bef41f07 $bef6e0cb $bef9a02d xr:$00000554= $befc5d27 $beff17b2 $bf00e7e4 $bf0242b1 xr:$00000558= $bf039c3d $bf04f484 $bf064b82 $bf07a136 xr:$0000055c= $bf08f59b $bf0a48ad $bf0b9a6b $bf0cead0 xr:$00000560= $bf0e39da $bf0f8784 $bf10d3cd $bf121eb0 xr:$00000564= $bf13682a $bf14b039 $bf15f6d9 $bf173c07 xr:$00000568= $bf187fc0 $bf19c200 $bf1b02c6 $bf1c420c xr:$0000056c= $bf1d7fd1 $bf1ebc12 $bf1ff6cb $bf212ff9 xr:$00000570= $bf226799 $bf239da9 $bf24d225 $bf26050a xr:$00000574= $bf273656 $bf286605 $bf299415 $bf2ac082 xr:$00000578= $bf2beb4a $bf2d1469 $bf2e3bde $bf2f61a5 xr:$0000057c= $bf3085bb $bf31a81d $bf32c8c9 $bf33e7bc xr:$00000580= $bf3504f3 $bf36206c $bf373a23 $bf385216 xr:$00000584= $bf396842 $bf3a7ca4 $bf3b8f3b $bf3ca003 xr:$00000588= $bf3daef9 $bf3ebc1b $bf3fc767 $bf40d0da xr:$0000058c= $bf41d870 $bf42de29 $bf43e200 $bf44e3f5 xr:$00000590= $bf45e403 $bf46e22a $bf47de65 $bf48d8b3 xr:$00000594= $bf49d112 $bf4ac77f $bf4bbbf8 $bf4cae79 xr:$00000598= $bf4d9f02 $bf4e8d90 $bf4f7a1f $bf5064af xr:$0000059c= $bf514d3d $bf5233c6 $bf531849 $bf53fac3 table b-1 x memory rom contents (full cycle of cosine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-4 DSP96002/d, rev. 2 motorola xr:$000005a0= $bf54db31 $bf55b993 $bf5695e5 $bf577026 xr:$000005a4= $bf584853 $bf591e6a $bf59f26a $bf5ac450 xr:$000005a8= $bf5b941a $bf5c61c7 $bf5d2d53 $bf5df6be xr:$000005ac= $bf5ebe05 $bf5f8327 $bf604621 $bf6106f2 xr:$000005b0= $bf61c598 $bf628210 $bf633c5a $bf63f473 xr:$000005b4= $bf64aa59 $bf655e0b $bf660f88 $bf66becc xr:$000005b8= $bf676bd8 $bf6816a8 $bf68bf3c $bf696591 xr:$000005bc= $bf6a09a7 $bf6aab7b $bf6b4b0c $bf6be858 xr:$000005c0= $bf6c835e $bf6d1c1d $bf6db293 $bf6e46be xr:$000005c4= $bf6ed89e $bf6f6830 $bf6ff573 $bf708066 xr:$000005c8= $bf710908 $bf718f57 $bf721352 $bf7294f8 xr:$000005cc= $bf731447 $bf73913f $bf740bdd $bf748422 xr:$000005d0= $bf74fa0b $bf756d97 $bf75dec6 $bf764d97 xr:$000005d4= $bf76ba07 $bf772417 $bf778bc5 $bf77f110 xr:$000005d8= $bf7853f8 $bf78b47b $bf791298 $bf796e4e xr:$000005dc= $bf79c79d $bf7a1e84 $bf7a7302 $bf7ac516 xr:$000005e0= $bf7b14be $bf7b61fc $bf7baccd $bf7bf531 xr:$000005e4= $bf7c3b28 $bf7c7eb0 $bf7cbfc9 $bf7cfe73 xr:$000005e8= $bf7d3aac $bf7d7474 $bf7dabcc $bf7de0b1 xr:$000005ec= $bf7e1324 $bf7e4323 $bf7e70b0 $bf7e9bc9 xr:$000005f0= $bf7ec46d $bf7eea9d $bf7f0e58 $bf7f2f9d xr:$000005f4= $bf7f4e6d $bf7f6ac7 $bf7f84ab $bf7f9c18 xr:$000005f8= $bf7fb10f $bf7fc38f $bf7fd397 $bf7fe129 xr:$000005fc= $bf7fec43 $bf7ff4e6 $bf7ffb11 $bf7ffec4 xr:$00000600= $bf800000 $bf7ffec4 $bf7ffb11 $bf7ff4e6 xr:$00000604= $bf7fec43 $bf7fe129 $bf7fd397 $bf7fc38f xr:$00000608= $bf7fb10f $bf7f9c18 $bf7f84ab $bf7f6ac7 xr:$0000060c= $bf7f4e6d $bf7f2f9d $bf7f0e58 $bf7eea9d xr:$00000610= $bf7ec46d $bf7e9bc9 $bf7e70b0 $bf7e4323 xr:$00000614= $bf7e1324 $bf7de0b1 $bf7dabcc $bf7d7474 xr:$00000618= $bf7d3aac $bf7cfe73 $bf7cbfc9 $bf7c7eb0 xr:$0000061c= $bf7c3b28 $bf7bf531 $bf7baccd $bf7b61fc xr:$00000620= $bf7b14be $bf7ac516 $bf7a7302 $bf7a1e84 xr:$00000624= $bf79c79d $bf796e4e $bf791298 $bf78b47b xr:$00000628= $bf7853f8 $bf77f110 $bf778bc5 $bf772417 xr:$0000062c= $bf76ba07 $bf764d97 $bf75dec6 $bf756d97 xr:$00000630= $bf74fa0b $bf748422 $bf740bdd $bf73913f table b-1 x memory rom contents (full cycle of cosine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables motorola DSP96002/d, rev. 2 b-5 xr:$00000634= $bf731447 $bf7294f8 $bf721352 $bf718f57 xr:$00000638= $bf710908 $bf708066 $bf6ff573 $bf6f6830 xr:$0000063c= $bf6ed89e $bf6e46be $bf6db293 $bf6d1c1d xr:$00000640= $bf6c835e $bf6be858 $bf6b4b0c $bf6aab7b xr:$00000644= $bf6a09a7 $bf696591 $bf68bf3c $bf6816a8 xr:$00000648= $bf676bd8 $bf66becc $bf660f88 $bf655e0b xr:$0000064c= $bf64aa59 $bf63f473 $bf633c5a $bf628210 xr:$00000650= $bf61c598 $bf6106f2 $bf604621 $bf5f8327 xr:$00000654= $bf5ebe05 $bf5df6be $bf5d2d53 $bf5c61c7 xr:$00000658= $bf5b941a $bf5ac450 $bf59f26a $bf591e6a xr:$0000065c= $bf584853 $bf577026 $bf5695e5 $bf55b993 xr:$00000660= $bf54db31 $bf53fac3 $bf531849 $bf5233c6 xr:$00000664= $bf514d3d $bf5064af $bf4f7a1f $bf4e8d90 xr:$00000668= $bf4d9f02 $bf4cae79 $bf4bbbf8 $bf4ac77f xr:$0000066c= $bf49d112 $bf48d8b3 $bf47de65 $bf46e22a xr:$00000670= $bf45e403 $bf44e3f5 $bf43e200 $bf42de29 xr:$00000674= $bf41d870 $bf40d0da $bf3fc767 $bf3ebc1b xr:$00000678= $bf3daef9 $bf3ca003 $bf3b8f3b $bf3a7ca4 xr:$0000067c= $bf396842 $bf385216 $bf373a23 $bf36206c xr:$00000680= $bf3504f3 $bf33e7bc $bf32c8c9 $bf31a81d xr:$00000684= $bf3085bb $bf2f61a5 $bf2e3bde $bf2d1469 xr:$00000688= $bf2beb4a $bf2ac082 $bf299415 $bf286605 xr:$0000068c= $bf273656 $bf26050a $bf24d225 $bf239da9 xr:$00000690= $bf226799 $bf212ff9 $bf1ff6cb $bf1ebc12 xr:$00000694= $bf1d7fd1 $bf1c420c $bf1b02c6 $bf19c200 xr:$00000698= $bf187fc0 $bf173c07 $bf15f6d9 $bf14b039 xr:$0000069c= $bf13682a $bf121eb0 $bf10d3cd $bf0f8784 xr:$000006a0= $bf0e39da $bf0cead0 $bf0b9a6b $bf0a48ad xr:$000006a4= $bf08f59b $bf07a136 $bf064b82 $bf04f484 xr:$000006a8= $bf039c3d $bf0242b1 $bf00e7e4 $beff17b2 xr:$000006ac= $befc5d27 $bef9a02d $bef6e0cb $bef41f07 xr:$000006b0= $bef15aea $beee9479 $beebcbbb $bee900b7 xr:$000006b4= $bee63375 $bee363fa $bee0924f $beddbe79 xr:$000006b8= $bedae880 $bed8106b $bed53641 $bed25a09 xr:$000006bc= $becf7bca $becc9b8b $bec9b953 $bec6d529 xr:$000006c0= $bec3ef15 $bec1071e $bebe1d4a $bebb31a0 xr:$000006c4= $beb8442a $beb554ec $beb263ef $beaf713a table b-1 x memory rom contents (full cycle of cosine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-6 DSP96002/d, rev. 2 motorola xr:$000006c8= $beac7cd4 $bea986c4 $bea68f12 $bea395c5 xr:$000006cc= $bea09ae5 $be9d9e78 $be9aa086 $be97a117 xr:$000006d0= $be94a031 $be919ddd $be8e9a22 $be8b9507 xr:$000006d4= $be888e93 $be8586ce $be827dc0 $be7ee6e1 xr:$000006d8= $be78cfcc $be72b651 $be6c9a7f $be667c66 xr:$000006dc= $be605c13 $be5a3997 $be541501 $be4dee60 xr:$000006e0= $be47c5c2 $be419b37 $be3b6ecf $be354098 xr:$000006e4= $be2f10a2 $be28defc $be22abb6 $be1c76de xr:$000006e8= $be164083 $be1008b7 $be09cf86 $be039502 xr:$000006ec= $bdfab273 $bdee3876 $bde1bc2e $bdd53db9 xr:$000006f0= $bdc8bd36 $bdbc3ac3 $bdafb680 $bda3308c xr:$000006f4= $bd96a905 $bd8a200a $bd7b2b74 $bd621469 xr:$000006f8= $bd48fb30 $bd2fe007 $bd16c32c $bcfb49ba xr:$000006fc= $bcc90ab0 $bc96c9b6 $bc490e90 $bbc90f88 xr:$00000700= $a48d4000 $3bc90f88 $3c490e90 $3c96c9b6 xr:$00000704= $3cc90ab0 $3cfb49ba $3d16c32c $3d2fe007 xr:$00000708= $3d48fb30 $3d621469 $3d7b2b74 $3d8a200a xr:$0000070c= $3d96a905 $3da3308c $3dafb680 $3dbc3ac3 xr:$00000710= $3dc8bd36 $3dd53db9 $3de1bc2e $3dee3876 xr:$00000714= $3dfab273 $3e039502 $3e09cf86 $3e1008b7 xr:$00000718= $3e164083 $3e1c76de $3e22abb6 $3e28defc xr:$0000071c= $3e2f10a2 $3e354098 $3e3b6ecf $3e419b37 xr:$00000720= $3e47c5c2 $3e4dee60 $3e541501 $3e5a3997 xr:$00000724= $3e605c13 $3e667c66 $3e6c9a7f $3e72b651 xr:$00000728= $3e78cfcc $3e7ee6e1 $3e827dc0 $3e8586ce xr:$0000072c= $3e888e93 $3e8b9507 $3e8e9a22 $3e919ddd xr:$00000730= $3e94a031 $3e97a117 $3e9aa086 $3e9d9e78 xr:$00000734= $3ea09ae5 $3ea395c5 $3ea68f12 $3ea986c4 xr:$00000738= $3eac7cd4 $3eaf713a $3eb263ef $3eb554ec xr:$0000073c= $3eb8442a $3ebb31a0 $3ebe1d4a $3ec1071e xr:$00000740= $3ec3ef15 $3ec6d529 $3ec9b953 $3ecc9b8b xr:$00000744= $3ecf7bca $3ed25a09 $3ed53641 $3ed8106b xr:$00000748= $3edae880 $3eddbe79 $3ee0924f $3ee363fa xr:$0000074c= $3ee63375 $3ee900b7 $3eebcbbb $3eee9479 xr:$00000750= $3ef15aea $3ef41f07 $3ef6e0cb $3ef9a02d xr:$00000754= $3efc5d27 $3eff17b2 $3f00e7e4 $3f0242b1 xr:$00000758= $3f039c3d $3f04f484 $3f064b82 $3f07a136 table b-1 x memory rom contents (full cycle of cosine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables motorola DSP96002/d, rev. 2 b-7 xr:$0000075c= $3f08f59b $3f0a48ad $3f0b9a6b $3f0cead0 xr:$00000760= $3f0e39da $3f0f8784 $3f10d3cd $3f121eb0 xr:$00000764= $3f13682a $3f14b039 $3f15f6d9 $3f173c07 xr:$00000768= $3f187fc0 $3f19c200 $3f1b02c6 $3f1c420c xr:$0000076c= $3f1d7fd1 $3f1ebc12 $3f1ff6cb $3f212ff9 xr:$00000770= $3f226799 $3f239da9 $3f24d225 $3f26050a xr:$00000774= $3f273656 $3f286605 $3f299415 $3f2ac082 xr:$00000778= $3f2beb4a $3f2d1469 $3f2e3bde $3f2f61a5 xr:$0000077c= $3f3085bb $3f31a81d $3f32c8c9 $3f33e7bc xr:$00000780= $3f3504f3 $3f36206c $3f373a23 $3f385216 xr:$00000784= $3f396842 $3f3a7ca4 $3f3b8f3b $3f3ca003 xr:$00000788= $3f3daef9 $3f3ebc1b $3f3fc767 $3f40d0da xr:$0000078c= $3f41d870 $3f42de29 $3f43e200 $3f44e3f5 xr:$00000790= $3f45e403 $3f46e22a $3f47de65 $3f48d8b3 xr:$00000794= $3f49d112 $3f4ac77f $3f4bbbf8 $3f4cae79 xr:$00000798= $3f4d9f02 $3f4e8d90 $3f4f7a1f $3f5064af xr:$0000079c= $3f514d3d $3f5233c6 $3f531849 $3f53fac3 xr:$000007a0= $3f54db31 $3f55b993 $3f5695e5 $3f577026 xr:$000007a4= $3f584853 $3f591e6a $3f59f26a $3f5ac450 xr:$000007a8= $3f5b941a $3f5c61c7 $3f5d2d53 $3f5df6be xr:$000007ac= $3f5ebe05 $3f5f8327 $3f604621 $3f6106f2 xr:$000007b0= $3f61c598 $3f628210 $3f633c5a $3f63f473 xr:$000007b4= $3f64aa59 $3f655e0b $3f660f88 $3f66becc xr:$000007b8= $3f676bd8 $3f6816a8 $3f68bf3c $3f696591 xr:$000007bc= $3f6a09a7 $3f6aab7b $3f6b4b0c $3f6be858 xr:$000007c0= $3f6c835e $3f6d1c1d $3f6db293 $3f6e46be xr:$000007c4= $3f6ed89e $3f6f6830 $3f6ff573 $3f708066 xr:$000007c8= $3f710908 $3f718f57 $3f721352 $3f7294f8 xr:$000007cc= $3f731447 $3f73913f $3f740bdd $3f748422 xr:$000007d0= $3f74fa0b $3f756d97 $3f75dec6 $3f764d97 xr:$000007d4= $3f76ba07 $3f772417 $3f778bc5 $3f77f110 xr:$000007d8= $3f7853f8 $3f78b47b $3f791298 $3f796e4e xr:$000007dc= $3f79c79d $3f7a1e84 $3f7a7302 $3f7ac516 xr:$000007e0= $3f7b14be $3f7b61fc $3f7baccd $3f7bf531 xr:$000007e4= $3f7c3b28 $3f7c7eb0 $3f7cbfc9 $3f7cfe73 xr:$000007e8= $3f7d3aac $3f7d7474 $3f7dabcc $3f7de0b1 xr:$000007ec= $3f7e1324 $3f7e4323 $3f7e70b0 $3f7e9bc9 table b-1 x memory rom contents (full cycle of cosine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-8 DSP96002/d, rev. 2 motorola xr:$000007f0= $3f7ec46d $3f7eea9d $3f7f0e58 $3f7f2f9d xr:$000007f4= $3f7f4e6d $3f7f6ac7 $3f7f84ab $3f7f9c18 xr:$000007f8= $3f7fb10f $3f7fc38f $3f7fd397 $3f7fe129 xr:$000007fc= $3f7fec43 $3f7ff4e6 $3f7ffb11 $3f7ffec4 table b-2 y memory rom contents (full cycle of sine values) yr:$00000400= $00000000 $3bc90f88 $3c490e90 $3c96c9b6 yr:$00000404= $3cc90ab0 $3cfb49ba $3d16c32c $3d2fe007 yr:$00000408= $3d48fb30 $3d621469 $3d7b2b74 $3d8a200a yr:$0000040c= $3d96a905 $3da3308c $3dafb680 $3dbc3ac3 yr:$00000410= $3dc8bd36 $3dd53db9 $3de1bc2e $3dee3876 yr:$00000414= $3dfab273 $3e039502 $3e09cf86 $3e1008b7 yr:$00000418= $3e164083 $3e1c76de $3e22abb6 $3e28defc yr:$0000041c= $3e2f10a2 $3e354098 $3e3b6ecf $3e419b37 yr:$00000420= $3e47c5c2 $3e4dee60 $3e541501 $3e5a3997 yr:$00000424= $3e605c13 $3e667c66 $3e6c9a7f $3e72b651 yr:$00000428= $3e78cfcc $3e7ee6e1 $3e827dc0 $3e8586ce yr:$0000042c= $3e888e93 $3e8b9507 $3e8e9a22 $3e919ddd yr:$00000430= $3e94a031 $3e97a117 $3e9aa086 $3e9d9e78 yr:$00000434= $3ea09ae5 $3ea395c5 $3ea68f12 $3ea986c4 yr:$00000438= $3eac7cd4 $3eaf713a $3eb263ef $3eb554ec yr:$0000043c= $3eb8442a $3ebb31a0 $3ebe1d4a $3ec1071e yr:$00000440= $3ec3ef15 $3ec6d529 $3ec9b953 $3ecc9b8b yr:$00000444= $3ecf7bca $3ed25a09 $3ed53641 $3ed8106b yr:$00000448= $3edae880 $3eddbe79 $3ee0924f $3ee363fa yr:$0000044c= $3ee63375 $3ee900b7 $3eebcbbb $3eee9479 yr:$00000450= $3ef15aea $3ef41f07 $3ef6e0cb $3ef9a02d yr:$00000454= $3efc5d27 $3eff17b2 $3f00e7e4 $3f0242b1 yr:$00000458= $3f039c3d $3f04f484 $3f064b82 $3f07a136 yr:$0000045c= $3f08f59b $3f0a48ad $3f0b9a6b $3f0cead0 yr:$00000460= $3f0e39da $3f0f8784 $3f10d3cd $3f121eb0 yr:$00000464= $3f13682a $3f14b039 $3f15f6d9 $3f173c07 yr:$00000468= $3f187fc0 $3f19c200 $3f1b02c6 $3f1c420c yr:$0000046c= $3f1d7fd1 $3f1ebc12 $3f1ff6cb $3f212ff9 yr:$00000470= $3f226799 $3f239da9 $3f24d225 $3f26050a yr:$00000474= $3f273656 $3f286605 $3f299415 $3f2ac082 table b-1 x memory rom contents (full cycle of cosine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables motorola DSP96002/d, rev. 2 b-9 yr:$00000478= $3f2beb4a $3f2d1469 $3f2e3bde $3f2f61a5 yr:$0000047c= $3f3085bb $3f31a81d $3f32c8c9 $3f33e7bc yr:$00000480= $3f3504f3 $3f36206c $3f373a23 $3f385216 yr:$00000484= $3f396842 $3f3a7ca4 $3f3b8f3b $3f3ca003 yr:$00000488= $3f3daef9 $3f3ebc1b $3f3fc767 $3f40d0da yr:$0000048c= $3f41d870 $3f42de29 $3f43e200 $3f44e3f5 yr:$00000490= $3f45e403 $3f46e22a $3f47de65 $3f48d8b3 yr:$00000494= $3f49d112 $3f4ac77f $3f4bbbf8 $3f4cae79 yr:$00000498= $3f4d9f02 $3f4e8d90 $3f4f7a1f $3f5064af yr:$0000049c= $3f514d3d $3f5233c6 $3f531849 $3f53fac3 yr:$000004a0= $3f54db31 $3f55b993 $3f5695e5 $3f577026 yr:$000004a4= $3f584853 $3f591e6a $3f59f26a $3f5ac450 yr:$000004a8= $3f5b941a $3f5c61c7 $3f5d2d53 $3f5df6be yr:$000004ac= $3f5ebe05 $3f5f8327 $3f604621 $3f6106f2 yr:$000004b0= $3f61c598 $3f628210 $3f633c5a $3f63f473 yr:$000004b4= $3f64aa59 $3f655e0b $3f660f88 $3f66becc yr:$000004b8= $3f676bd8 $3f6816a8 $3f68bf3c $3f696591 yr:$000004bc= $3f6a09a7 $3f6aab7b $3f6b4b0c $3f6be858 yr:$000004c0= $3f6c835e $3f6d1c1d $3f6db293 $3f6e46be yr:$000004c4= $3f6ed89e $3f6f6830 $3f6ff573 $3f708066 yr:$000004c8= $3f710908 $3f718f57 $3f721352 $3f7294f8 yr:$000004cc= $3f731447 $3f73913f $3f740bdd $3f748422 yr:$000004d0= $3f74fa0b $3f756d97 $3f75dec6 $3f764d97 yr:$000004d4= $3f76ba07 $3f772417 $3f778bc5 $3f77f110 yr:$000004d8= $3f7853f8 $3f78b47b $3f791298 $3f796e4e yr:$000004dc= $3f79c79d $3f7a1e84 $3f7a7302 $3f7ac516 yr:$000004e0= $3f7b14be $3f7b61fc $3f7baccd $3f7bf531 yr:$000004e4= $3f7c3b28 $3f7c7eb0 $3f7cbfc9 $3f7cfe73 yr:$000004e8= $3f7d3aac $3f7d7474 $3f7dabcc $3f7de0b1 yr:$000004ec= $3f7e1324 $3f7e4323 $3f7e70b0 $3f7e9bc9 yr:$000004f0= $3f7ec46d $3f7eea9d $3f7f0e58 $3f7f2f9d yr:$000004f4= $3f7f4e6d $3f7f6ac7 $3f7f84ab $3f7f9c18 yr:$000004f8= $3f7fb10f $3f7fc38f $3f7fd397 $3f7fe129 yr:$000004fc= $3f7fec43 $3f7ff4e6 $3f7ffb11 $3f7ffec4 yr:$00000500= $3f800000 $3f7ffec4 $3f7ffb11 $3f7ff4e6 yr:$00000504= $3f7fec43 $3f7fe129 $3f7fd397 $3f7fc38f yr:$00000508= $3f7fb10f $3f7f9c18 $3f7f84ab $3f7f6ac7 table b-2 y memory rom contents (full cycle of sine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-10 DSP96002/d, rev. 2 motorola yr:$0000050c= $3f7f4e6d $3f7f2f9d $3f7f0e58 $3f7eea9d yr:$00000510= $3f7ec46d $3f7e9bc9 $3f7e70b0 $3f7e4323 yr:$00000514= $3f7e1324 $3f7de0b1 $3f7dabcc $3f7d7474 yr:$00000518= $3f7d3aac $3f7cfe73 $3f7cbfc9 $3f7c7eb0 yr:$0000051c= $3f7c3b28 $3f7bf531 $3f7baccd $3f7b61fc yr:$00000520= $3f7b14be $3f7ac516 $3f7a7302 $3f7a1e84 yr:$00000524= $3f79c79d $3f796e4e $3f791298 $3f78b47b yr:$00000528= $3f7853f8 $3f77f110 $3f778bc5 $3f772417 yr:$0000052c= $3f76ba07 $3f764d97 $3f75dec6 $3f756d97 yr:$00000530= $3f74fa0b $3f748422 $3f740bdd $3f73913f yr:$00000534= $3f731447 $3f7294f8 $3f721352 $3f718f57 yr:$00000538= $3f710908 $3f708066 $3f6ff573 $3f6f6830 yr:$0000053c= $3f6ed89e $3f6e46be $3f6db293 $3f6d1c1d yr:$00000540= $3f6c835e $3f6be858 $3f6b4b0c $3f6aab7b yr:$00000544= $3f6a09a7 $3f696591 $3f68bf3c $3f6816a8 yr:$00000548= $3f676bd8 $3f66becc $3f660f88 $3f655e0b yr:$0000054c= $3f64aa59 $3f63f473 $3f633c5a $3f628210 yr:$00000550= $3f61c598 $3f6106f2 $3f604621 $3f5f8327 yr:$00000554= $3f5ebe05 $3f5df6be $3f5d2d53 $3f5c61c7 yr:$00000558= $3f5b941a $3f5ac450 $3f59f26a $3f591e6a yr:$0000055c= $3f584853 $3f577026 $3f5695e5 $3f55b993 yr:$00000560= $3f54db31 $3f53fac3 $3f531849 $3f5233c6 yr:$00000564= $3f514d3d $3f5064af $3f4f7a1f $3f4e8d90 yr:$00000568= $3f4d9f02 $3f4cae79 $3f4bbbf8 $3f4ac77f yr:$0000056c= $3f49d112 $3f48d8b3 $3f47de65 $3f46e22a yr:$00000570= $3f45e403 $3f44e3f5 $3f43e200 $3f42de29 yr:$00000574= $3f41d870 $3f40d0da $3f3fc767 $3f3ebc1b yr:$00000578= $3f3daef9 $3f3ca003 $3f3b8f3b $3f3a7ca4 yr:$0000057c= $3f396842 $3f385216 $3f373a23 $3f36206c yr:$00000580= $3f3504f3 $3f33e7bc $3f32c8c9 $3f31a81d yr:$00000584= $3f3085bb $3f2f61a5 $3f2e3bde $3f2d1469 yr:$00000588= $3f2beb4a $3f2ac082 $3f299415 $3f286605 yr:$0000058c= $3f273656 $3f26050a $3f24d225 $3f239da9 yr:$00000590= $3f226799 $3f212ff9 $3f1ff6cb $3f1ebc12 yr:$00000594= $3f1d7fd1 $3f1c420c $3f1b02c6 $3f19c200 yr:$00000598= $3f187fc0 $3f173c07 $3f15f6d9 $3f14b039 yr:$0000059c= $3f13682a $3f121eb0 $3f10d3cd $3f0f8784 table b-2 y memory rom contents (full cycle of sine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables motorola DSP96002/d, rev. 2 b-11 yr:$000005a0= $3f0e39da $3f0cead0 $3f0b9a6b $3f0a48ad yr:$000005a4= $3f08f59b $3f07a136 $3f064b82 $3f04f484 yr:$000005a8= $3f039c3d $3f0242b1 $3f00e7e4 $3eff17b2 yr:$000005ac= $3efc5d27 $3ef9a02d $3ef6e0cb $3ef41f07 yr:$000005b0= $3ef15aea $3eee9479 $3eebcbbb $3ee900b7 yr:$000005b4= $3ee63375 $3ee363fa $3ee0924f $3eddbe79 yr:$000005b8= $3edae880 $3ed8106b $3ed53641 $3ed25a09 yr:$000005bc= $3ecf7bca $3ecc9b8b $3ec9b953 $3ec6d529 yr:$000005c0= $3ec3ef15 $3ec1071e $3ebe1d4a $3ebb31a0 yr:$000005c4= $3eb8442a $3eb554ec $3eb263ef $3eaf713a yr:$000005c8= $3eac7cd4 $3ea986c4 $3ea68f12 $3ea395c5 yr:$000005cc= $3ea09ae5 $3e9d9e78 $3e9aa086 $3e97a117 yr:$000005d0= $3e94a031 $3e919ddd $3e8e9a22 $3e8b9507 yr:$000005d4= $3e888e93 $3e8586ce $3e827dc0 $3e7ee6e1 yr:$000005d8= $3e78cfcc $3e72b651 $3e6c9a7f $3e667c66 yr:$000005dc= $3e605c13 $3e5a3997 $3e541501 $3e4dee60 yr:$000005e0= $3e47c5c2 $3e419b37 $3e3b6ecf $3e354098 yr:$000005e4= $3e2f10a2 $3e28defc $3e22abb6 $3e1c76de yr:$000005e8= $3e164083 $3e1008b7 $3e09cf86 $3e039502 yr:$000005ec= $3dfab273 $3dee3876 $3de1bc2e $3dd53db9 yr:$000005f0= $3dc8bd36 $3dbc3ac3 $3dafb680 $3da3308c yr:$000005f4= $3d96a905 $3d8a200a $3d7b2b74 $3d621469 yr:$000005f8= $3d48fb30 $3d2fe007 $3d16c32c $3cfb49ba yr:$000005fc= $3cc90ab0 $3c96c9b6 $3c490e90 $3bc90f88 yr:$00000600= $80000000 $bbc90f88 $bc490e90 $bc96c9b6 yr:$00000604= $bcc90ab0 $bcfb49ba $bd16c32c $bd2fe007 yr:$00000608= $bd48fb30 $bd621469 $bd7b2b74 $bd8a200a yr:$0000060c= $bd96a905 $bda3308c $bdafb680 $bdbc3ac3 yr:$00000610= $bdc8bd36 $bdd53db9 $bde1bc2e $bdee3876 yr:$00000614= $bdfab273 $be039502 $be09cf86 $be1008b7 yr:$00000618= $be164083 $be1c76de $be22abb6 $be28defc yr:$0000061c= $be2f10a2 $be354098 $be3b6ecf $be419b37 yr:$00000620= $be47c5c2 $be4dee60 $be541501 $be5a3997 yr:$00000624= $be605c13 $be667c66 $be6c9a7f $be72b651 yr:$00000628= $be78cfcc $be7ee6e1 $be827dc0 $be8586ce yr:$0000062c= $be888e93 $be8b9507 $be8e9a22 $be919ddd yr:$00000630= $be94a031 $be97a117 $be9aa086 $be9d9e78 table b-2 y memory rom contents (full cycle of sine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-12 DSP96002/d, rev. 2 motorola yr:$00000634= $bea09ae5 $bea395c5 $bea68f12 $bea986c4 yr:$00000638= $beac7cd4 $beaf713a $beb263ef $beb554ec yr:$0000063c= $beb8442a $bebb31a0 $bebe1d4a $bec1071e yr:$00000640= $bec3ef15 $bec6d529 $bec9b953 $becc9b8b yr:$00000644= $becf7bca $bed25a09 $bed53641 $bed8106b yr:$00000648= $bedae880 $beddbe79 $bee0924f $bee363fa yr:$0000064c= $bee63375 $bee900b7 $beebcbbb $beee9479 yr:$00000650= $bef15aea $bef41f07 $bef6e0cb $bef9a02d yr:$00000654= $befc5d27 $beff17b2 $bf00e7e4 $bf0242b1 yr:$00000658= $bf039c3d $bf04f484 $bf064b82 $bf07a136 yr:$0000065c= $bf08f59b $bf0a48ad $bf0b9a6b $bf0cead0 yr:$00000660= $bf0e39da $bf0f8784 $bf10d3cd $bf121eb0 yr:$00000664= $bf13682a $bf14b039 $bf15f6d9 $bf173c07 yr:$00000668= $bf187fc0 $bf19c200 $bf1b02c6 $bf1c420c yr:$0000066c= $bf1d7fd1 $bf1ebc12 $bf1ff6cb $bf212ff9 yr:$00000670= $bf226799 $bf239da9 $bf24d225 $bf26050a yr:$00000674= $bf273656 $bf286605 $bf299415 $bf2ac082 yr:$00000678= $bf2beb4a $bf2d1469 $bf2e3bde $bf2f61a5 yr:$0000067c= $bf3085bb $bf31a81d $bf32c8c9 $bf33e7bc yr:$00000680= $bf3504f3 $bf36206c $bf373a23 $bf385216 yr:$00000684= $bf396842 $bf3a7ca4 $bf3b8f3b $bf3ca003 yr:$00000688= $bf3daef9 $bf3ebc1b $bf3fc767 $bf40d0da yr:$0000068c= $bf41d870 $bf42de29 $bf43e200 $bf44e3f5 yr:$00000690= $bf45e403 $bf46e22a $bf47de65 $bf48d8b3 yr:$00000694= $bf49d112 $bf4ac77f $bf4bbbf8 $bf4cae79 yr:$00000698= $bf4d9f02 $bf4e8d90 $bf4f7a1f $bf5064af yr:$0000069c= $bf514d3d $bf5233c6 $bf531849 $bf53fac3 yr:$000006a0= $bf54db31 $bf55b993 $bf5695e5 $bf577026 yr:$000006a4= $bf584853 $bf591e6a $bf59f26a $bf5ac450 yr:$000006a8= $bf5b941a $bf5c61c7 $bf5d2d53 $bf5df6be yr:$000006ac= $bf5ebe05 $bf5f8327 $bf604621 $bf6106f2 yr:$000006b0= $bf61c598 $bf628210 $bf633c5a $bf63f473 yr:$000006b4= $bf64aa59 $bf655e0b $bf660f88 $bf66becc yr:$000006b8= $bf676bd8 $bf6816a8 $bf68bf3c $bf696591 yr:$000006bc= $bf6a09a7 $bf6aab7b $bf6b4b0c $bf6be858 yr:$000006c0= $bf6c835e $bf6d1c1d $bf6db293 $bf6e46be yr:$000006c4= $bf6ed89e $bf6f6830 $bf6ff573 $bf708066 table b-2 y memory rom contents (full cycle of sine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables motorola DSP96002/d, rev. 2 b-13 yr:$000006c8= $bf710908 $bf718f57 $bf721352 $bf7294f8 yr:$000006cc= $bf731447 $bf73913f $bf740bdd $bf748422 yr:$000006d0= $bf74fa0b $bf756d97 $bf75dec6 $bf764d97 yr:$000006d4= $bf76ba07 $bf772417 $bf778bc5 $bf77f110 yr:$000006d8= $bf7853f8 $bf78b47b $bf791298 $bf796e4e yr:$000006dc= $bf79c79d $bf7a1e84 $bf7a7302 $bf7ac516 yr:$000006e0= $bf7b14be $bf7b61fc $bf7baccd $bf7bf531 yr:$000006e4= $bf7c3b28 $bf7c7eb0 $bf7cbfc9 $bf7cfe73 yr:$000006e8= $bf7d3aac $bf7d7474 $bf7dabcc $bf7de0b1 yr:$000006ec= $bf7e1324 $bf7e4323 $bf7e70b0 $bf7e9bc9 yr:$000006f0= $bf7ec46d $bf7eea9d $bf7f0e58 $bf7f2f9d yr:$000006f4= $bf7f4e6d $bf7f6ac7 $bf7f84ab $bf7f9c18 yr:$000006f8= $bf7fb10f $bf7fc38f $bf7fd397 $bf7fe129 yr:$000006fc= $bf7fec43 $bf7ff4e6 $bf7ffb11 $bf7ffec4 yr:$00000700= $bf800000 $bf7ffec4 $bf7ffb11 $bf7ff4e6 yr:$00000704= $bf7fec43 $bf7fe129 $bf7fd397 $bf7fc38f yr:$00000708= $bf7fb10f $bf7f9c18 $bf7f84ab $bf7f6ac7 yr:$0000070c= $bf7f4e6d $bf7f2f9d $bf7f0e58 $bf7eea9d yr:$00000710= $bf7ec46d $bf7e9bc9 $bf7e70b0 $bf7e4323 yr:$00000714= $bf7e1324 $bf7de0b1 $bf7dabcc $bf7d7474 yr:$00000718= $bf7d3aac $bf7cfe73 $bf7cbfc9 $bf7c7eb0 yr:$0000071c= $bf7c3b28 $bf7bf531 $bf7baccd $bf7b61fc yr:$00000720= $bf7b14be $bf7ac516 $bf7a7302 $bf7a1e84 yr:$00000724= $bf79c79d $bf796e4e $bf791298 $bf78b47b yr:$00000728= $bf7853f8 $bf77f110 $bf778bc5 $bf772417 yr:$0000072c= $bf76ba07 $bf764d97 $bf75dec6 $bf756d97 yr:$00000730= $bf74fa0b $bf748422 $bf740bdd $bf73913f yr:$00000734= $bf731447 $bf7294f8 $bf721352 $bf718f57 yr:$00000738= $bf710908 $bf708066 $bf6ff573 $bf6f6830 yr:$0000073c= $bf6ed89e $bf6e46be $bf6db293 $bf6d1c1d yr:$00000740= $bf6c835e $bf6be858 $bf6b4b0c $bf6aab7b yr:$00000744= $bf6a09a7 $bf696591 $bf68bf3c $bf6816a8 yr:$00000748= $bf676bd8 $bf66becc $bf660f88 $bf655e0b yr:$0000074c= $bf64aa59 $bf63f473 $bf633c5a $bf628210 yr:$00000750= $bf61c598 $bf6106f2 $bf604621 $bf5f8327 yr:$00000754= $bf5ebe05 $bf5df6be $bf5d2d53 $bf5c61c7 yr:$00000758= $bf5b941a $bf5ac450 $bf59f26a $bf591e6a table b-2 y memory rom contents (full cycle of sine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-14 DSP96002/d, rev. 2 motorola yr:$0000075c= $bf584853 $bf577026 $bf5695e5 $bf55b993 yr:$00000760= $bf54db31 $bf53fac3 $bf531849 $bf5233c6 yr:$00000764= $bf514d3d $bf5064af $bf4f7a1f $bf4e8d90 yr:$00000768= $bf4d9f02 $bf4cae79 $bf4bbbf8 $bf4ac77f yr:$0000076c= $bf49d112 $bf48d8b3 $bf47de65 $bf46e22a yr:$00000770= $bf45e403 $bf44e3f5 $bf43e200 $bf42de29 yr:$00000774= $bf41d870 $bf40d0da $bf3fc767 $bf3ebc1b yr:$00000778= $bf3daef9 $bf3ca003 $bf3b8f3b $bf3a7ca4 yr:$0000077c= $bf396842 $bf385216 $bf373a23 $bf36206c yr:$00000780= $bf3504f3 $bf33e7bc $bf32c8c9 $bf31a81d yr:$00000784= $bf3085bb $bf2f61a5 $bf2e3bde $bf2d1469 yr:$00000788= $bf2beb4a $bf2ac082 $bf299415 $bf286605 yr:$0000078c= $bf273656 $bf26050a $bf24d225 $bf239da9 yr:$00000790= $bf226799 $bf212ff9 $bf1ff6cb $bf1ebc12 yr:$00000794= $bf1d7fd1 $bf1c420c $bf1b02c6 $bf19c200 yr:$00000798= $bf187fc0 $bf173c07 $bf15f6d9 $bf14b039 yr:$0000079c= $bf13682a $bf121eb0 $bf10d3cd $bf0f8784 yr:$000007a0= $bf0e39da $bf0cead0 $bf0b9a6b $bf0a48ad yr:$000007a4= $bf08f59b $bf07a136 $bf064b82 $bf04f484 yr:$000007a8= $bf039c3d $bf0242b1 $bf00e7e4 $beff17b2 yr:$000007ac= $befc5d27 $bef9a02d $bef6e0cb $bef41f07 yr:$000007b0= $bef15aea $beee9479 $beebcbbb $bee900b7 yr:$000007b4= $bee63375 $bee363fa $bee0924f $beddbe79 yr:$000007b8= $bedae880 $bed8106b $bed53641 $bed25a09 yr:$000007bc= $becf7bca $becc9b8b $bec9b953 $bec6d529 yr:$000007c0= $bec3ef15 $bec1071e $bebe1d4a $bebb31a0 yr:$000007c4= $beb8442a $beb554ec $beb263ef $beaf713a yr:$000007c8= $beac7cd4 $bea986c4 $bea68f12 $bea395c5 yr:$000007cc= $bea09ae5 $be9d9e78 $be9aa086 $be97a117 yr:$000007d0= $be94a031 $be919ddd $be8e9a22 $be8b9507 yr:$000007d4= $be888e93 $be8586ce $be827dc0 $be7ee6e1 yr:$000007d8= $be78cfcc $be72b651 $be6c9a7f $be667c66 yr:$000007dc= $be605c13 $be5a3997 $be541501 $be4dee60 yr:$000007e0= $be47c5c2 $be419b37 $be3b6ecf $be354098 yr:$000007e4= $be2f10a2 $be28defc $be22abb6 $be1c76de yr:$000007e8= $be164083 $be1008b7 $be09cf86 $be039502 yr:$000007ec= $bdfab273 $bdee3876 $bde1bc2e $bdd53db9 table b-2 y memory rom contents (full cycle of sine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables motorola DSP96002/d, rev. 2 b-15 yr:$000007f0= $bdc8bd36 $bdbc3ac3 $bdafb680 $bda3308c yr:$000007f4= $bd96a905 $bd8a200a $bd7b2b74 $bd621469 yr:$000007f8= $bd48fb30 $bd2fe007 $bd16c32c $bcfb49ba yr:$000007fc= $bcc90ab0 $bc96c9b6 $bc490e90 $bbc90f88 table b-2 y memory rom contents (full cycle of sine values) (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x and y memory rom tables b-16 DSP96002/d, rev. 2 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/ affirmative action employer. how to reach us: usa/europe/locations not listed : motorola literature distribution p.o. box 20912 phoenix, arizona 85036 1 (800) 441-2447 or 1 (602) 303-5454 mfax : rmfax0@email.sps.mot.com touchtone (602) 244-6609 asia/pacific : motorola semiconductors h.k. ltd. 8b tai ping industrial park 51 ting kok road tai po, n.t., hong kong 852-2662928 technical resource center: 1 (800) 521-6274 dsp helpline dsphelp@dsp.sps.mot.com japan : nippon motorola ltd. tatsumi-spd-jldc 6f seibu-butsuryu-center 3-14-2 tatsumi koto-ku tokyo 135, japan 03-3521-8315 internet : http://www.motorola-dsp.com once and mfax are trademarks of motorola, inc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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